Research On ZedBoard Implementation Of Low Bit Rate Speech Algorithm

Under the condition that bandwidth resources are increasingly precious,low bit rate speech encoding technology become an important research direction as a result of low bandwidth resource usage.In many low bit speech encoding algorithms,the mixed excitation linear prediction(MELP)algorithm is talent showing itself due to its outstanding performance and is used as the federal government of the United States in the 2.4Kbps standard algorithm.When applying the encoding algorithm to the actual implementation,the platform has an important influence on its performance.At present,most researchers choose to use digital signal processor(DSP)and field programmable gate array(FPGA)to do the research of low bit rate speech encoding.Among them,FPGA,because of its flexibility and rich embedded resources,is playing an increasingly important role.The Zed Board series,which is launched by Xilinx company,with its abundant resources and sufficient peripheral,become more and more favored by researchers.The aim of this article is to achieve a low bit rate speech encoding system on the Zed Board development board.As a result of low bit rate speech algorithm's high computational complexity,so the real-time performance is often not easy to be satisfied.While the FPGA can do parallel computation and it is very flexible,makes it very suitable for the realization of low bit rate speech encoding algorithm.In many low bit rate speech algorithms,this paper choose the MELP algorithm because of its better performanc and the higher complexity as the research target.Reducing the occipancy rate and using less to complete the whole MELP encoding system while satisfying the real-time performance of this algorithm.In this paper,the principle and calculate flow of MELP algorithm are first studied in depth.Next studied the development process,design ideas and optimization methods of FPGA and Zed Board.Combine the characteristics of FPGA,to optimize the MELP algorithm.Then use high-level synthesis tools to implement each module from bottom to top.Reduce the amount of calculations without affecting the final result,and accelerate the algorithm with the help of appropriate parallel computing tools,ultimately achieving a balance between time and resource consumption.When the various modules are connected to top level,two schemes of similar logic and minimum computation unit multiplexing are proposed,and the reuse of hardware resources is reduced again by increasing the use of the underlying arithmetic unit as much as possible,thereby improving the utilization rate of the arithmetic unit.Combining the driver of the underlying digital-to-analog conversion chip implemented in the hardware description language(HDL),a MELP coding system with low resource occupancy rate and high speed is realized.This article finally achieved MELP encoding algorithm on Zed Board development board.The linear prediction calculation unit,vector quantization unit,and filters in MELP can be transplanted into other low bit rate speech coding algorithms,which has certain versatility.Compared with traditional implementation methods such as DSP,FPGA+ARM,the method used in this paper has higher resource utilization and consumes less resources because it is closer to the bottom layer.At the same time,the inter-module optimization methods proposed in this paper hava certain versatility and can be applied in similar high-level integrated design.