Research On Key Technologies Of High Level Synthesis On FPGA For Cryptographic Application

High-performance computing is undergoing fundamental changes. Demand for power cost and heat dissipation is becoming a bottleneck to limit large data centers expanding. These changes promote the continuous development of new high-performance computing technology. Programmable logic array technology is a possible increase performance while reducing power consumption technology. But FPGA development faces multiple challenges in the development of parallel hardware applications, so we need to be more easily FPGA programming tools to tap the potential of high-performance computing. High-level synthesis(HLS) technology items described high-level language into a hardware description language. The introduction of HLS greatly reduce the workload of the designer and significantly shorten the design cycle and improve module reuse.This paper presents the design of data-driven high-level synthesis method based on the library of application IP cores. We design a system framework can be achieved, but also to ensure that this system is not only easy to use but also capable of generating a high-performance cryptographic hardware code. The encryption algorithm becomes parameterized reconfigurable FPGA IP cores. Based on the software flow and IP core library, using the searching algorithm to generate and optimize the hardware node graph. Finally, depending on the hardware node diagrams, we generate Verilog code.This paper constructs efficient IP core library, representation and realization of IP core is the basis of hardware accelerator. We use the data structure to describe the behavior of these hardware attributes and computing IP core, to generate a flow chart of the search algorithm provides hardware IP core. In this paper, a typical cryptographic algorithm implemented by hardware, and thus build a high-performance application-oriented password encryption template library. Also, for the fearture program,such as loops, branches and other structures designed the corresponding parameter module.This paper studies the optimization algorithm for the hardware data flow diagram. According to the front-end data flow diagram, we generated hardware flow diagram by using hardware modules bound algorithm. Based on hardware flow diagram for the module, the paper by reusing modules to reduce resource consumption pipeline; using common subexpression elimination, to optimize the branch structure; the use of algorithms to achieve the best area to explore the design space.Finally, this paper build a FPGA prototype system to verify the proposed high-level synthesis framework. We integrated the pipeline generated by the proposed HLS framwork with top-level control modules of the target platform together into an FPGA. Finally, advanced multiple applications were examples and achieve performance comparison results showed that high-level synthesis and optimization framework of this paper has a good effect.