Physical Design And Low Power CTS For Passive UHF RFID Chip

RFID(Radio Frequency Identification) is a technology that incorporates the use of electromagnetic or electrostatic coupling in the radio frequency (RF) portion of the electromagnetic spectrum to uniquely identify an objects. The UHF (Ultra High Frequency) RFID technology makes use of electromagnetic to gain the power for chip, which has the advantages of long operating distance, large quantity of information, high speed and low cost, and it has been hot currently in at home and broad. For the application demand of UHF RFID chip, our research mainly focuses on low power architecture design, low power CTS and physical implication, based on ISO/IEC18000-6C international standard.Firstly, the power model corresponding to each component in CMOS circuits in ASIC/SOC was introduced and the dynamic and static method for power estimation was summarized. Then, we analyzed the methods which has been used in the industry to low power and explained the focal and difficult points in detail.Secondly, to meet the demand of protocol and application for digital baseband, a new low power architecture was provided, which contained a power manger unit to control the clock input of internal modules. The pipelined mode and clock gating effectively decreased the total power and resolve too high peak power consumption.Thirdly, the solution and application for UHF RFID chip which take advantage of Synopsys Astro physical design tool, based on TSMC0.18u m low power standard cell library, was elaborated in the paper. This included floorplan, timing constraint, placement, CTS, route and DFM.Finally, the principle of clock tree’s power consumption was elaborated. Focused on structure of UHF RFID complicated clock tree to reduce the total power and cost, by analyzing many power and area reports, we firmed up the best solution, after finishing CTS, physical design and integral power analysis many times. The solution for clock tree has been approved effectively in reducing total power by20%-30%in our chip test after tap-out.