Design And Physical Implementation Of Low-Power RFID IP Core With SPI Interface

The internet of things have been payed high attention by worldwide countries and promoted by our country's policy. In this case, the key technology RFID is also developing rapidly. It is mainly composed of reader and tag. The tag chip which forms the tag become an important core technology due to the high design difficulty and the great market demand.Along with the continuous development of integrated circuits, the power consumption has become an important factor restricting product performance. Especially for passive UHF RFID chip, the great internal power results in relatively small chip identification distance, limiting the further development and application of passive chip. To address this problem, this paper research for the method of reducing the power consumption of passive UHF RFID tag chip based on national standard air interface protocol. Taking into account the concept of IP core reuse, the RFID IP core digital baseband design architecture with SPI interface has been put forward in this paper in order to be directly called to design, greatly reducing the error rate and the complexity of the design.Firstly, based on UHF RFID chip communication protocol and SPI communication theory, this paper divide the digital baseband into six modules by function combined with the actual needs of the system. The function of each module and the advantage over modules in original architecture is described in detail. Then this paper introduces the power consumption of CMOS circuit and the methods by the SPEC file modification and gated clock to reduce design power according to power estimation formula. Among the methods, which kind of buffer to choose in CTS is the key to reducing the power of the clock network. CLKINV has been proven to build the clock tree network as clock cell in this design with lower power consumption and better skew balancing effect.Then, by using the NC-Verilog simulation verification the coding to ensure that the design can achieve normal function according to protocol requirements and logic integrated circuit is completed by DC. This paper introduces Encounter-based low-power layout at SMIC 0.13 um process in detail to achieve the reusable RFID IP core.Finally, we conducted a timing verification, physical verification and simulation verification and proved the design is timing closure, have no physical design rules and layout consistency violation and can work to achieve proper function. The total power consumption of the proposed low-power IP cores in this paper is 11.43?w, this total area of design digital baseband is 91901.78?m2, got a 17.5% reduction in power consumption and got a 19.6% reduction in area compared to the previous digital baseband. Therefore the low-power RFID IP core with SPI interface proposed in the paper not only is able to select suitable memory for system integration design based on the actual design requirements, but also has lower power consumption and can achieve higher performance.