Design Of Digital Baseband Of RFID Chip With Encryption Algorithm Based On Independent Standard

The Radio Frequency Identification(RFID)is a technology that wirelessly identifies and transmits information to specific targets through the coupling between spatial electric fields and magnetic field signals.The communication process does not require physical or optical contact between the items.The advantage of wireless contact makes it not affected by harsh environments and weather in practical applications.In addition,the tag has so many advantages such as high recognition speed,large storage capacity,reusability that make RFID technology widely used in logistics,transportation,anti-counterfeiting,military,medical and other fields.With the rapid development of mobile payment,smart home and the rise of new information warfare in recent years,the security of RFID systems has become increasingly prominent.Once information leakage occurs,it will cause serious losses.Therefore,enhancing the security of RFID systems is of great significance for the large-scale popularization of this technology.The design goal of this paper is to embed the encryption algorithm into the digital baseband based on the passive RF air interface protocol to complete the encrypted communication between the reader and the tag.On the basis of satisfying the protocol,the layout of the chip is completed through logic synthesis and physical implementation,and the digital baseband power consumption of the design is 20%better than the existing baseband,and the area is optimized by 5%.Aiming at the security tag chip that meets the air interface standard issued in 2011,the first part of the military radio frequency identification air interface:800/900MHz,on the basis of in-depth analysis of the security authentication and secure communication protocols,a variety of key encryption algorithms are compared and analyzed.Based on Pipeline structure and loop iterative structure,a design structure of SM4 encryption algorithm is proposed,which realizes better optimization of power consumption and area.Based on the TSMC 0.18?m 7T technology library,the logic synthesis of the circuit was completed using Design Compiler of Synopsys.The design results show that the final power consumption is 1.66?w and the area is 29738?m~2.Based on the integrated application of clock gating and gray code coding technology,the digital baseband design of the tag chip with embedded SM4 encryption algorithm is completed.The circuit simulation results show that the digital baseband functionality meets design requirements.The simulation results of low-power logic synthesis show that the designed digital baseband overall power consumption is 14.5?w,the area is 202586?m~2,optimized by 27.5%and 8%respectively,and the expected goal is achieved.Based on the SoC Encounter of Cadence,the overall physical implementation of the tag chip including the digital baseband is implemented.Low-power clock tree synthesis is achieved by combining medium-sized buffer and inverter,reducing clock tree power consumption by 20%.The parasitic parameters of the overall layout of the tag chip are extracted,and the SPEF file is obtained.The static timing analysis of the tag chip is performed by Prime Time.Based on the Calibre of Mentor Graphics,the DRC and LVS verification of the overall layout of the tag chip was completed.The simulation results show that the results meet the design requirements.