Research And Design Of CMOS Distributed Amplifier

With the development of wireless communication technology to high frequency broadband,monolithic microwave integrated circuits(MMIC)have important practical value as a part of wireless broadband communication systems.As a vital branch of MMIC,CMOS distributed amplifiers have become a hot research topic in the field of industry and academia,for their simple structure,high gain bandwidth,flat gain in-band and good impedance matching simultaneously.This thesis introduces the conventional distributed amplifier topology and research methods.For the design specifications of wideband power amplifiers and wideband low noise amplifiers,a distributed power amplifier(DPA)and two distributed low noise amplifiers(DLNA)are proposed in different CMOS technologies.A non-uniform four-stage DPA is designed and implemented in the standard 0.18 ?m CMOS technology.The proposed amplifier is designed with a combination of increasing the gain cell size step by step and decreasing the inductance of the drain artificial transmission line(ATL).On the premise of maintaining good input and output impedance matching,the output power and efficiency in broadband are improved.Measurement results show that the amplifier achieves an average gain of 9 dB from 1 to 17.2 GHz band,together with the input return loss is less than – 8.5 dB and the output return loss is less than – 8 dB.The output power at 1 dB output compression point range from 7.8 dBm to 10.5 dBm,and the corresponding power added efficiency is from 3.6% to 6.2%.Two type of uniform DLNAs are designed and completed in 65 nm CMOS technology.In the gain cell circuit of three-stage DLNA,the current reuse technique is adopted to improve the gain,and noise cancelling technique is used to reduce the noise while realizing the single to double conversion of the signal.The noise performance of amplifier is further improved by using resistive-inductive network load at the gate ATL terminal.The gain cell circuit of the two-stage DLNA also uses current reuse technique and noise cancelling technique to improve the gain and noise performance.MOS capacitors are used as the bypass capacitance of the gate and drain ATLs to reduce the layout area of the amplifier.Simulation results show that the three-stage DLNA achieves 24.2 dB average in the frequency band from 0.5 to 5.7 GHz,and the minimum noise figure is 2.7 dB.The two-stage DLNA achieves 25 dB average in the frequency band from 0.5 to 4.1 GHz,and the minimum noise figure is only 2.5 dB.Moreover,both DLNAs maintain good input impedance matching and linearity.