Interface For MEMS Accelerometer With Digital Self-Test

With the rapid development of Micro-Electron Mechanical System(MEMS)sensors,their products have largely affected our daily lives.Among them,accelerometer sensors are widely used,but for military application,the accuracy of commonly used accelerometers is far from enough,and the self-test function can not meet the requirements.Through research and analysis,this paper designs a high-precision MEMS accelerometer interface circuit with digital self-test function.This paper firstly introduces the working principle and the non-ideal characteristics of the accelerometer,and establishes the mathematical model of the system in the SIMULINK toolbox.The transistor-level design and simulation of the circuit is completed according to the mathematical model,and finally based on the high voltage 0.35?m CMOS process,the layout of the circuit was drawn.In the interface,the discrete PID control circuit is used to ensure the stability of the accelerometer interface circuit,and realize the high loop gain of the overall closed-loop system,thus reducing the odd harmonic of the signal,which improves the accuracy of the signal detection.Combined with high-voltage process,a larger detection range is achieved by increasing the electrostatic force feedback voltage.The paper uses digital resonator to generate high-precision 1-bit sinusoidal signal stream with sigma-delta modulation.The signal-to-noise ratio of the self-test signal can reach 120dB,which is higher than the acceleration signal imitated by the existing mechanical vibration table.And it avoids the design of low distortion DAC.Therefore,the self-detection accuracy of the accelerometer harmonic distortion is ensured,and the capacitance mismatch is evaluated by self-detecting the magnitude of the even harmonic of the output signal spectrum.By compensating the mismatch,the harmonic distortion of the system can be decreased.In the circuit simulation,the interface circuit was given a sinusoidal acceleration signal with an amplitude of 2g.The harmonic distortion of the power spectral density(PSD)of the output signal is-130dB,and the signal-to-noise ratio(SNR)reaches 112dB,and the equivalent acceleration noise is 149.38ng/,Hz.In the self-test simulation,when the sensitive structure has a capacitance mismatch of 0.2pF,the second harmonic amplitude of the output signal is-118dB,which is much higher than the noise floor,and complete self-test of the accelerometer harmonic distortion..Finally,the high-voltage 035?m CMOS process is used to draw the layout of the analog part of the interface,and the Design Compiler(DC)and Encounter are used to perform netlist synthesis and layout the digital circuit,and finally complete the layout of the overall accelerometer With a 2g sinusoidal acceleration input,the SNR of the output stream is 105dB,and the equivalent acceleration noise is 325.69ng/Hz realizing the high accuracy of acceleration detection.In self-test simulation,the second harmonic distortion component is-117dB when the capacitance mismatch is O.2pF,which can clearly distinguish t the sensor harmonic distortion.