Silicon-Based On-Chip Spiral Inductors Simulation And Its Application In True-Time Delay

With the increasing development of integrated circuit technology and the rapid growth of mobile communication market,radio frequency integrated circuit based on CMOS process has been widely used.True-time delay lines based on CMOS technology have the advantages of low power consumption,low cost,and high integration.As a key module of the phased array antenna,real-time delay line design is crucial.Planar spiral inductor is needed in many important subelement of the radio frequency integrated circuit.Since the inductor performance directly affects the performance of the unit circuit and even the whole system,it is of great significance to improve the quality factor and build an accurate physically-based model at high frequency of on-chip spiral inductor.Firstly,this thesis introduce the basic characteristics of on-chip spiral inductor and the multiple loss mechanism and high frequency effect of planar spiral inductor are analyzed in detail.Then,the influence of the geometric parameters of the planar spiral inductor on its performance is mainly studied through HFSS electromagnetic field simulation and the design flow and optimization rules of on-chip spiral inductor are summarized.A true time delay operating over 8GHz to 36 GHz has been designed with planar spiral inductor based on 65 nm CMOS process.The coarse adjustment delay module has 3 stages,and the delay difference between adjacent delay units is 5ps.The digital control unit controls the analog path selector to realize the selection og the signal path.The fine adjustment module realizes a 5ps continuous adjustable delay to ensure that the delay difference of the coarse adjustment of the adjacent delay units is completely covered,and the delay control is completed by changing the control voltage of the variable capacitor.The entire circuit layout design is completed using Cadence Virtuoso layout-editor and the main performance indexes of true time delay are simulated based on Spectre simulator.The simulated results are given below: in the operating frequency bandwidth,the maximum relative delay is 15 ps with less than 11% delay variation and the input and output return loss is better than-10 dB.The insertion loss is-18.6±0.2dB at 20 GHz.The proposed TTD core occupies 840?m×780?m,respectively.