Optimization And Design Of On-chip Stacked Spiral Inductor

With the development of information and communication science and technology, the requirement of miniaturization, integration and low consumption of mobile communication module becomes much higher. Wireless transceiver is the core structure of a mobile communication module, which includes RF primary loop, low-noise amplifier, voltage-controlled oscillator and intermediate-frequency filter.The performance of these modules such as gain, noise factor, power dissipation all have great relationship of inductor. The higher quality factor the passive inductors have, the better performance the module will achieve. Therefore, how to integrate the inductor into a chip which is compatible with CMOS process and realize low power dissipation and high performance is the key of RF integrated circuits.The conventional planar inductors occupy a large area of the whole RF circuits. Nevertheless, stacked inductor can reduce the area of chip with the same inductance remained. But compared with planar ones, stacked inductors contain more coupling capacity between adjacent metal layers, which cause the decrease of performance and thus restrain their application in RF circuits. Based on the analysis of parasitic effect and mechanism of loss of inductor, a new stratified stacked inductor has been proposed. Compared with the conventional stacked ones, the distance of adjacent metal layers of the proposed tacked inductors doubled. Thus the parasitic capacity has been reduced and the quality factor and self-resonant frequency become higher. The simulation results show that the Q and fSR have been enhanced about15%and87%with the inductance remained at3.4nH.In order to prove the optimization of the proposed stacked inductors,3low-pass filters have been designed with the conventional and proposed ones respectively. The simulation results all displayed that the performance of LPF with proposed stacked inductors is better than it with conventional ones.This paper is funded by the sub-project of the national Ministry of science and technology major projects(core high based)——45nm complete sets of product process and IP-1(2009ZX02023-2-1).