Analysis And Optimization Of On-Chip Spiral Inductors For Ultra-wideband Low Noise Amplifier

In recent years, the rapid development of wireless business and integrated circuit technology make the radio frequency integrated circuit developed greatly. As the main components of the radio frequency integrated circuit, inductor have a significant impact on the performance of the radio frequency integrated circuit. As the most widely used on-chip inductor, on-chip spiral inductor has large area and low quality factor, its performance will directly affect the overall performance of the circuit. Therefore, the study the analysis of on-chip spiral inductor have a profound significance.In this paper, the basic definition and performance indicators of on-chip spiral inductors are firstly introduced, and the loss mechanism and high frequency parasitic effects of spiral inductor on chip are detailedly investigated. The impact of process and structure parameters on the performance of inductance is studied. Several innovative form of on-chip spiral inductor are optimal designed, which are graded inductor, multiple-current-path inductor and differential solenoidal inductor. We propose a novel inductor layout structure with graded metal line width and space in order to produce the high frequency parasitic resistance of the inner inductor. The graded inductors have a good performance. The maximum Q of the graded inductor has 17% improvement under its inductance fixed. In order to reduce the influence of skin effect and proximity effect on inductor, the metal strips of inductor are divided into multi-shunt tracks and are abreasted at the port of inductor. Both the direct current parasitic resistance and high frequency parasitic resistance of the multiple- current-path inductor have a little value. We propose a improved inductor with varying route to reduce the interlayer parasitic capacitance. As a result the self resonance frequency increases by about 4.5GHz.With the JAZZ 0.18 um Si Ge proeess, the ultra-wideband low noise amplifier(LNA) is designed, its performance parameters and circuit structure are described. The graded inductor proposed in this paper is used to design the wideband low noise amplifier circuit. The influence of the improved inductor on the LNA performance is compared. The graded structure is used in the inductor of input matching network, it can effectively reduce the parasitic resistance and reduce the high frequency noise figure; the graded inductor has a good high frequency performance, the circuit which iscomposed with the graded inductor can achieve a good high frequency impedance matching; the graded structure is also used in the parallel peak structure of load, with low parasitic capacitance, the structure can improve the circuit gain and gain flatness. Results show that the graded inductor can effectively improve the high frequency performance of low noise amplifier. The simulation results showed that the input reflection coefficient is less than-16 d B, reverse isolation is less than-50 d B, power gain is 21.75±0.45 d B, output reflection coefficient is less than-15 d B, noise figure is less than-15 d B.