A High-Speed Adder-Front Carry Adder Research And Design

Interger addition is one of the most elementary and important operations, and adder is the most elementary and casual arithmetic operation unit. What is more, the average computation time is one of the significant reasons of slowing down the operation speed of IC (Integrated Circuits). Therefore the design of high-speed adder circuit is very essential.In this thesis, to improve the performance of the adder, full-custom design is used to implement the design of submodels and the optimization of prefix-carrying addition algorithm. Though the full-custom design costs longer period, and with low effenciency, it is characterized by its flexiblity in design, and importantly, it could improve the performance of adders dramatically.In this thesis, the entire arithmetic is firstly presented,and it makes comparison between the traditional addition algorithm and the prefix-carrying addition algorithm. Then to implement the prefix-carrying addition algorithm, carry lookahead signals (bit/block carry lookahead generate signal, bit/block carry lookahead kill signal, bit/block carry lookahead propagate signal) based on the dot operation are described in details, three kinds of tree-like circuits based on 32 bit Kogge-Stone(KS) tree,32 bit Han-Carlson(HC) tree, and 32 bit Brent-Kung(BK) tree are cennected, optimized respectively. Their delay time and transistor count are compared after optimization. The resutlts show that KS tree has the largest transistor count and shortest delay time, BK tree has the least transistor count and longest delay time, the transistor count and delay time; and the HC tree stays in the middle.In this thesis, the charge leakage (keeper) circuit is used to implement the design of submodel circuitry, that is to say, the prefix-carrying signals generation unit prefix-carrying tree unit, and the sum unit. During the process to build the prefix-carrying tree, domino logic and self-timed techology is used to decrease competion and risks, to make the best of clock, implementing the function of the adder.Based on XB0.35um process in the Cadecnce platform, three kinds of 32 bit tree-like CMOS prefix-carrying adders are designed. The simulation tool Spectre is ued to simulate the circuit and verify its function. The simulation results show that the maximum propagation delay time of the 32 bit HC tree-like prefix-carrying adder,32 bit BK tree-like prefix-carrying adder,32 bit KS tree-like prefix-carrying adder is 6.15ns,6.47ns, and 5.56ns which are 7.54,7.11 and 8.11 times faster than that of the traditional ripple-carry adder, which is 52.5ns.