The Research And Implementation Of The Downlink Low Complexity Signal Detection Algorithm In 5G System

In order to better meet the future application scenarios of “Ultra-Large Capacity” and “All-In-One”,the 5th generation mobile communication technology(5G)has become the mainstream trend of mobile communication.At present,many companies such as Huawei,Ericsson,and Samsung have entered the relevant testing phase of commercial deployment of 5G systems.With the introduction of a series of 5G new technologies such as Large-Scale Antennas,Advanced Coding and Modulation,Ultra-Dense Networking and High-Band Wireless Transmission,the related technical problems need to be solved urgently.This thesis is based on the national science and technology major project “Enhanced Mobile Broadband 5G Terminal Simulator”,and refers to the 5G protocol standard.Aiming at the channel estimation and signal detection of the downlink receiver in 5G system,some related algorithms are studied and simulated.The implementation verification of the project is based on the baseband processing platform which combines field programmable gate array(FPGA)and multi-core digital sgnal processor(DSP).The main innovations and work are as follows:1.Based on the de-modulation reference signal(DMRS),the channel estimation algorithm is studied and analyzed in 5G system.The method of combining the leastsquares(LS)algorithm and the first-order linear interpolation algorithm is used to design the FPGA scheme.2.In this thesis two kinds of multi-antenna transmission modes,transmission diversity and space division multiplexing,are analyzed and introduced.The signal detection algorithm in space division multiplexing mode is mainly studied.According to the multi-antenna technology and the project requirements,a sphere-decoding detection algorithm assisted by lattice reduction is proposed for the implementation of FPGA in space division multiplexing mode.3.According to the requirement of cooperative processing between FPGA and multicore DSP for data after channel estimation and signal detection in the project.Datainteraction scheme between processors based on serial rapid input output(SRIO)is designed and tested to get through the 5G downlink baseband processing link.4.The test results show that it takes 0.8925 ms for the baseband platform to complete the channel estimation and signal detection process when single sub-frame data is processed with 100 M system bandwidth.After signal detection the mean error vector magnitude(EVM)results is 2.64% and the peak EVM results is 8.77%.The resource consumption rate of the selected FPGA chip is 41%,which can meet the testing requirements of project at this stage.This thesis focuses on the research and improvement of 5G downlink signal detection algorithm.The module is designed in detail by using the hardware description language and applied in practical project.At the same time,Through the ModelSim function simulation and Chipscope on-board test the correctness of the scheme is verified.Finally the rationality of the scheme is verified by timing analysis and resource consumption.