Design And Implementation Of FPGA Algorithm For GPS/Beidou Satellite Navigation Signal Simulator

The satellite signal simulator can accurately generate the simulated satellite signal according to the motion scenes set by users,which provides a test tool for the research and development of satellite signal receivers.This paper mainly focuses on the hardware design of GPS / Beidou satellite navigation signal simulator and the algorithm and software design of signal simulator in FPGA.The main job is as follows:1.The hardware design of the satellite signal simulator is based on the digital model of GPS / Beidou satellite IF signal.The hardware architecture of "DSP + FPGA" is adopted in the baseband signal processing part.DSP is used to complete the generation of navigation message and the calculation of control parameters.The data communication of interface and the generated algorithm of baseband signal is mainly designed and implemented in FPGA.2.In algorithm evaluating stage,the design of the satellite simulator on the experimental platform is completed.The generation of signal verifies the feasibility of the hardware design of satellite signal simulator.The design of the satellite simulator on the engineering platform which is an upgrade of experimental platform is completed.The FPGA part completes the design of the generated module of the pseudo random code and the generated module of IF carrier signal.It focused on the design of the algorithm of code NCO and carrier NCO which generate the pseudo random code and subcarrier with doppler shift.According to the algorithm of DSP,the satellite signal's initial parameters are calculated.It is used to set the initial delay and align the satellite signal,which can ensure the realization of accurate pseudoranges.Multi-channel satellite signals' selected output is realized in FPGA.Not only the design of receiving and reading of navigation message,but also signal modulated function is realized in FPGA.The design complete the interface between FPGA and other modules,such as EMIF interface,SRIO interface,PCIe interface.Those interfaces are debugged in hardware and software and the cache solution of those interfaces is designed to buffer incoming data.3.Building the signal simulator receiving and testing environment,the software receiver is used to analysis the positioning accuracy of the collected digital IF signal.On the other hand,a hardware receiver is used to capture and track the signal.Then the positioning accuracy is analyzed to verify the feasibility of the proposed scheme.