FPGA-based 40G Ethernet Interface Design

The rapid development of computer network technology has stimulated the development of various fields.Information collection work from a small amount of storage,display and other functions,gradually become a large number of data acquisition,real-time signal display and processing direction.Therefore,network transmission is not only limited to local area network,but also to metropolitan area network and Wan area.From the beginning of June 2010 for the official release of the standard protocol IEEE802.3ba 40 G / 100 G Ethernet interfaces,the major domestic and foreign companies have been competing to launch 40 G / 100 G Ethernet products.Thus,Ethernet products is of great significance and economic value,and its development without delay.Based on the FPGA platform,this thesis designs the 40 G Ethernet interface.According to the IEEE 802.3 BA protocol,we first understand the composition of the interface from the Ethernet architecture and realize the normal transmission of the data frame through the Ethernet data frame type,Ethernet transmission and reception specifications,and support full duplex communication.Then the MAC layer controller is divided into control sending module,control receiving module,40Gb/s Media Independent Interface(XLGMII)module and flow control module by modular design.Round Robin Scheduling algorithm is used to distribute and encode the data sending and receiving for the speed of 40Gb/s,and XLGMII interface is used to connect the data link layer and physical layer.Finally,congestion on the transmission link is managed by traffic control strategy.Each module is set forth in the design,and it is divided into several sub modules for complex modules.In the design,the overall design scheme is given first,and then each module is interpreted separately,including interface signal,state transition diagram,flow chart,schematic diagram and so on.This thesis uses Verilog HDL language to build a verification platform based on FPGA to verify the functions of each module,including transceiver,packet detection,flow control and so on.At the same time,using ChipScope in Xilinx ISE Design Suite tool,the design is verified by FPGA,and the verification results meet the design requirements.This thesis designs a 40 G Ethernet interface based on the standard protocol IEEE802.3ba,and verifies that the design has higher interconnection speed,clock frequency and wider and more reasonable internal parallel structure by using FPGA.It has certain practical significance and economic value.