Design Of 400Gbps Ultrahigh Speed Ethernet Interface Based On IEEE802.3bs

Rapid growth of data traffic will be caused by the popularization of smart terminals and mobile devices with video streaming,as well as the further application of Io T technology and 5th generation mobile networks.The bandwidth capacity of 100 gbps will be not enough.IEEE802.3bs standard for media access control parameters,physical layers,and management parameters for 200 Gbps and 400 Gbps Operation was approved by IEEE-SA Standards Board in december 2017.400 Gbps is the trend of Ethernet.As a part of IEEE802.3bs,Media Access Control(MAC)and Physical Coding Layer(PCS)are studied and implemented.The parallel self synchronization scramble algorithm is implemented in the logic design of PCS to reduce the clock frequency of high bandwidth scrambling operation.Reed Solomon(RS)encoding and decoding algorithm RS(514,544)are implemented by linear feedback shift register(LFSR)to check and correct data.In addition,Time stamp module which supports IEEE1588 time synchronization technology is designed for the interface.A verification platform based on universal verification methodology is built to simulate the design function.Field Programmable Gate Array(FPGA)chip of Intel Stratix 10 GX and Spirent Testcenter provide more real network environment for testing and verifing.As a result,the interface forward protocol data correctly and there is no data lose or be error when the network bandwidth is 400 Gbps and clock frequency is 390.625 MHz.The 400 Gbps interface designed in this dissertation meets the basic function requirements of IEEE802.3bs,with the feasibility of achieving.It provides a reference for the application of 400 Gbps Ethernet interface in the field of ultra-high speed bandwidth data center.