High-speed Load Balancing Algorithm Of The Fpga Implementation

In order to monitor the dataflow to improve the network security, safety monitoring equipment such as a firewall or IDS/IPS should be used. But as the network speed increasing, single device cannot stand apparently and nowday security devices are disturibed by the problems like data loss rate and low detecting rate. To resolve the problems above, the load balanced approach emerged as the times require. This thesis was on 2.5G high speed internet environment, adopting a load balanced algorithm which could distribute the 2.5G dataflow to four gbe port to monitor the flow on high-speed link.To make up the flaw of low balanced measurement of present load balance arithmetic, a HBDC algorithm combined by hash static balance and dynamic self-adaptable balance was discussed. The algorithm managed to achieve the fuction of load balance and ensure the balanced measurement less than 18%. The main task of this article was accomplishing the FPGA logic design,test,implementing and optimizing the existent algorithms. Using Quartus II,Modelsim and IXIA instrument to design and validate the arithmetic. The result shows that this load balance arithmetic can be applied to the system of monitoring the high-speed network abroad.The researchful contents of this article are as follows:1. Choose the right FPGA according to the complexity of the load balanced algorithm of the subject and software agreement and hardware design requested.2. Complete the verilog coding, simulation and implementation in Modelsim. Imporved the code and the algorithm until it satisfied the system demand according to the simulation result.3. Verified the logic of the load balance arithmetic and optimized system capability with the tool of SignalTap II and IXIA instrument. The result showed that the equipoise target reached to 18% at least, stisfying the system's request, as well as the data loss rate.