Design Of High Speed JPEG Decoder For Motion Posture Video Measurement Analyzer

Videogrammetric Measurement,as an interdisciplinary subject integrating traditional photogrammetry,optical measurement,machine vision and digital image processing analysis,three-dimensional reconstruction,has the advantages of strong environmental adaptability,non-contact,and high frequency response,especially in high speed wind tunnel testing.Videogrammetric measurrement for wind tunnel test is research focus at home and abroad because it has no special requirements on the test model.In order to improve the measurement accuracy,the camera resolution and frame rate used in videogrammetric measurement are getting higher and higher.How to process the high speed image data brought by high resolution and high frame rate in real time,become one of the problems to be solved in the videogrammetric measurement of high speed moving targets.In order to solve the problem of real-time encoding and decoding of high speed image data,research on key technologies of high speed decoders is carried out.Based on the analysis of the motion posture videogrammetric measurement analyzer implementation architecture and decoder interface and scheduling buffer resource constraints,combined with the subject design indicators and the JPEG decoder system structure,a topdown and modular design method was adopted to complete the overall architecture design and key technology analysis of the high speed JPEG decoder.Aiming at the high-throughput design index of the subject,based on the analysis of the JPEG decoding algorithm,the high throughput implementation scheme design of each functional module of the high speed decoder and the performance verification based on MATLAB have been completed.Aiming at the problem of the decoding efficiency of serial Huffman decoding and the low processing rate of 2D-IDCT transformation,based on the analysis of the coding law of Huffman coding table and the fast algorithm of 2D-IDCT transformation,technologies such as parallel pipeline processing architecture and ping-pong operation are adopted.Designed a high speed Huffman decoding algorithm based on parallel and pipeline architecture and an FPGA implementation architecture for fast 2D-IDCT transformation.Based on the FPGA implementation of the high speed JPEG decoder,the RTL-level design and system integration of the various functional modules of the decoder are completed based on the Verilog hardware description language.In order to verify the performance of the high speed JPEG decoder,a high speed JPEG decoder performance test platform was built.The test results show that the high speed JPEG decoder designed in this paper can achieve image JPEG decoding with a throughput rate of 2.105GB/s,and has good flexibility and scalability.