Design Of Network-on-chip For Reconfigurable Computing Processor

Reconfigurable processor is a new processor architecture which has significantadvantage compared with single-core processor, ASICs and FPGA. It is an importantdevelopment orientation of circuit structure. There are abundant computingresources in reconfigurable processor so that the chip scale is very large and itmakes great demands on the communication capabilities of the system. Traditionalon-chip bus can hardly meet the communication requirements of reconfigurableprocessor and network-on-chip will be the main communication structure. In orderto find the best NoC structure for reconfigurable processor, researchers need asimulator to build different system models quickly to test their communicationperformance and make a comparison.A cycle-accurate NoC simulator was designed and implemented in this thesiswith SoC Designer as the design platform. The simulator supports three differenttopologies:2D-Mesh, Ring and Spidergon. Several kinds of parameters can beconfigured, such as buffer depth and the number of virtual channels. The interfaceof network matches the AMBA-AHB protocol and it is therefore easy to integrate avariety of devices in the component library of SoC Designer. The simulator cancalculate two important performance parameters: throughput and average delay.Based on the two performance parameters, designer can quickly evaluate theperformance of the system with different NoC structure and make thecorresponding choice. In this thesis,8-node and16-node networks have been builtrespectively with the three topologies. Performance of different network arecalculated and compared with each other. In addition, the influence of data packetlength, buffer depth and the number of virtual channels on the performance ofnetwork was discussed. This thesis made a preliminary exploration for the use ofNoC in reconfigurable computing area.