| Reconfigurable preocessor combines the efficiency of ASIC and the flexibility of GPP,it can be well applied to the field of video processing with the characteristics of high computation complexity and parallel degree.Therefore,the advantages of parallel computing can be fully played and the research of visual information processing system based on reconfigurable way has always been a hotspot.This thesis first introduces the architecture,workflow and data flow of the visual information system based on reconfigurable preocessor.Then presents the structure and output sequence of the data source and discusses the interface scheme between main processing system and reconfigurable processor of the data and the control information.Designs the key circuit modules of main processing system: including the bridge circuit of I2 C and UART to PLB,realizes the communication between main processing system and other system;the DDR controller which realizes image frame caching in the DDR memory.In addition,the Retinex image enhancement algorithm is decomposed parallel and mapped on the array of the reconfigurable processor.Meanwhile,this thesis proposes a fast implemented Random Sprays Retienx method,which is more suitable for the areas with higher speed requirements.All the circuits designed in this thesis is simulated on Modelsim and verified on the platform of FPGA.Retinex algorithm is tested on Intel ATOM 230 test platform for its serial computing ability,and reconfigurable processor simulation test platform based on SoCD designer for its parallel computing ability.The result demonstrates that the computation efficiency using parallel method is 4.13 times more efficient than that of serial method.Experimental results based on MATLAB show that,the color coefficient,entropy and standard deviation of the result image enhanced by the proposed method are almost the same as those of the result image enhanced by the original RSR,but the speed of the proposed method is 25.6 times faster. |
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