Study Of IP Core And Integration Technique

With the development of Very Large Scale Integrated Circuit manufacturing process, the circuit scale increases larger and larger, the design complexity becomes more serious, and SoC becomes the main trend. One key technique is IP design and reuse.Based on top-down design method, the thesis discusses IP's SoC design and integration technique. The thesis consists of three parts:1.The thesis designs an IIS (Inter-IC Sound) IP, which introduces IIS interface bus and its protocol in detail and performs RTL level simulation and logic synthesis.2.Then, the thesis introduces a 32-bit embedded microprocessor hard IP, C*CORE C310. The thesis proposed a new back-end design method, which is a design flow combines Physical Compiler and Silicon Ensemble effectively.3.Following this, the thesis discusses the integration of C*CORE and IIS soft IP. An IP package method based on Finite State Machine is proposed.Except for design methodology and technique, some comprehensive experiments are performed. These experiments use some EDA tools, including functional simulation with Cadence's Verilog XL, logic synthesis with Synopsys's Design Compiler. The C310 hard IP has been taped out on SMIC 0.18um, and the test result satisfied requirements successfully.