| Residue Number System (RNS) is a non-weighted system, which results in carry free arithmetic operation and supports parallel high-speed concurrent computations. Addition, subtraction, and multiplication are carried out on each residue digit concurrently and independently.; So far, almost all the RNS based DSP algorithms were implemented in semi or full custom methods involving long turnaround time and high costs. It is highly desirable to produce ASICs for RNS based DSP algorithms with minimum cost and manufacturing time. Since FPGAs offer those advantages, this thesis investigates the applicability of FPGAs and other programmable logic devices for RNS based applications. This involves generation, simulation and synthesis of VHDL code using WVO, Altera Maxplus-II, FPGAExpress and LeonardoSpectrum as design environments. Altera's Max 7000 family and Flex 10K device families were considered for implementing RNS mod-5 and mod-15 multipliers, which were based on a three-stage architecture and best devices were determined based on area and delay optimizations, speed effect and device family architecture. |
