Researches On Key Techniques Of VLSI Implementation For Digital Signal Processing Based On Residue Number System

With the complexity increase of communication and signal processing technologies, especially in mobile terminals, airborne, and satellite-borne equipments, Digital Signal Processing (DSP) devices are required to provide higher and higher processing performance. The application specific DSP chips based on Very Large Scale Integration (VLSI) circuits are irreplaceable in high speed and complicated signal processing, such as source coding, channel decoding, demodulating, and signal transforming, etc. However, the conflicts among area, power consumption, and delay in VLSI chips become more and more prominent. Parallel processing is an effective approach for this problem. Residue Number System (RNS) is a non-weighted parallel number system which can improve the performance of the processing elements in traditional parallel processors. In this dissertation, the key issues in VLSI implementation of RNS-based DSP scheme, such as radix selection, modulo addition, scaling, and RNS detection issues, are discussed for DSP systems. This dissertation intends to provide an alternative to alleviate the conflicts between power consumption and processing speed of VLSI chips.The radix form of RNS is the primary factor for the complexity of RNS-based DSP systems. In Chapter 3, the definitions of parallelism degree and balance quality among RNS channels for moduli sets are proposed firstly. Then, the dynamic utilization ratio, parallelism degree, balance quality, and the modulo adder complexity of common radixes are analyzed for reference in radix selection. Moreover, a multi-channel moduli set composed of 2n,2n-1, and 2n-2k-1 is proposed. On the other hand, modulo adder is the fundamental component in RNS operations. In order to promote the application of the multi-channel moduli set proposed in Chapter 3, a universal algorithm and VLSI architecture based on carry correction and parallel prefix operations for modulo 2k-2k-1 adder is proposed in Chapter 4. Performance analysis results show that the "area* delay" performance of the proposed modulo adder is more efficient than that of traditional methods.Scaling is another important issue in RNS-based DSP systems, since it is one of the major manners to avoid overflow in computing procedure. In Chapter 5, the universal parallel VLSI architectures of signed RNS integers for any type of scaling factor are proposed firstly, in which a key correction constant is used to simplify the circuit design. Then, an updating algorithm is presented for redundant residue digit used in base extension of scaling and the VLSI implementation of power-of-two scaling is performed with specific moduli set. Furthermore, the high efficient scaling module for moduli set {2n-1,2n,2n+1} is also proposed. Accordingly, the research on this moduli set is more comprehensive. Finally, a 2" scaling-based residue to binary (R/B) converter is proposed, in which the maximum operation bit width is smaller than n. This method helps to eliminate the bottle-neck for the R/B conversion.Due to the non-weighted property of RNS, the magnitude comparison, sign detection, parity checking, and overflow detection are not as simple as those in TCS. However, they are the basic operations in signal processing, such as the threshold detection in communication receiver. In this dissertation, these four issues in RNS are grouped as detection issues. First, Chapter 6 gives the internal relations of the detection issues and the approaches to the others by any one of the four issues implementation. Then, a parity checking algorithm along with related propositions and certifications based on the celebrated Chinese Remainder Theory (CRT) and Mixed Radix Conversion (MRC) for the moduli set {2n-1,2n+1,22n+1} is proposed. The parity checker consists of two modular adders and a carry look-ahead chain. The hardware implementation requires less area and time delay.In Chapter 7 of this dissertation, a Finite Impulse Response (FIR) filter and the VLSI architectures of the key modules of Orthogonal Frequency Division Multiplexing (OFDM) demodulator are designed based on RNS. The two examples indicate that RNS-based schemes can reduce the critical path and area of DSP devices.