Design Of RSA Encryption Circute Based On Residue Number System

In secure system,RSA is mature public-key cryptography at present,it can encrypt,make a scratch of digital and validate degree.Residue number system(RNS) has been used to promote efficiency of RSA Encryption algorithms due to its inherent parallelism, modularity, and free-carry properties. The following researches on RNS RSA Encryption are proposed:This paper do researches on 1024-bit RSA encryption circute based on Residue Number System,and using RNS Binary scanning modulo exponentiation algorithm to implement encryption.So two groups 16-modulo set with dynamic range 1024-bit are choosed. sixteen principles obeyed in the selection of moduli set are proposed. Two RNS bases {264, 264+1, 264-1, 264-24+1, 264-26+1, 264-28+1, 264-210+1, 264-212+1, 264-214+1, 264-218+1, 264-220+1, 264-224+1, 264-228+1, 264-230+1, 265-1, 267-1},{264-22-1, 264-24-1, 264-25-1,264-27-1, 264-28-1, 264-210-1, 264-211-1, 264-216-1, 264-217-1, 264-219-1,264-220-1, 264-223-1,264-224-1, 264-226-1, 264-229-1, 264-231-1} is used to design RNS RSA encryption circute in this paper. Each modulus has the form of 2n,2n±1 or 2n-2k±1,these moduli forms make the hardware implementation of modular arithmetic easier and more efficient.To promote the arithmetic performance of RNS RSA encryption circute, high-speed adders adopt parellel prefix computation of carry chain has been researched. Aimed at modulo 2n-1 adders with double representations of zero, a modulo 2n-1 addition algorithm with a single representation of zero is proposed.Based on an efficient and high-speed diminished-1 modulo 2n+1 multiplication algorithm,a modulo 2n+1 multipliers use weighted representation is proposed,which avoid conversing between diminished-1and binary. Moduli set with the form of 2n-2k-1can offer excellent balance among the RNS channels for multi-channels RNS processing. In this paper, a novel algorithm and its VLSI implementation structureare proposed for modulo 2n-2k-1 multipliers. Based on the existing algorithm of modulo multiplier.Designing RSA encryption circute based on Residue Number System using Verilog HDL hardware circuite desciription,and contrast texts the correctness of the design between Modesim and Maple.and integration on Stratix IV FPGA.