The Research And FPGA Implementation Of The Downlink In LTE-A User Simulator System

The Long Term Evolution-Advanced(LTE-A)system,as the mainstream in the development of current wireless communication,has been used more and more widely in scenarios of high capacity and large connectivity.A wide range of mobile communication test solutions for the system are also available.However,there are few test solutions for device capacity and shock resistance;meanwhile,most of the market share goes to international telecommunications vendors.Considering the fact that the equipment designed by domestic manufacturers,when compared with the advanced equipment,has relatively limited functions and a wide gap and that some technical problems in the design of the baseband system are hard to solve,it is vital to conduct research on the equipment of the user equipment(UE)simulator.In this thesis,the aims of studying the downlink signal processing flow of terminal simulator system,and designing and implementing the downlink receiver by taking advantages of parallel execution of the Field Programmable Gate Array(FPGA)are achieved on the basis of the project of “Research on key technologies of LTE-A Multi-UE base station load and capacity test”,“LTE-A downlink signal processing FPGA and DSP software” and in combination with the LTE-A system protocol standard.The main innovations and work are as follows:1.The focuses of this thesis are the research and performance analysis of the channel estimation algorithm in LTE-A system.The method of combining the least-squares algorithm and the first-order linear interpolation algorithm is used to design the FPGA scheme.2.The signal detection algorithms for transmission diversity mode and space division multiplexing mode are studied and analyzed.According to the actual project requirements,FPGA design of the Space Frequency Block Code algorithm in transmission diversity mode is carried out.At the same time,extend on the basis of the project,a FPGA scheme based on the greedy strategy of sphere decoding detection algorithm in spatial multiplexing mode is designed.3.In this thesis,the signal processing flow of physical broadcast channel,physical control format indicator channel and physical downlink shared channel of the system are studied and designed.A Turbo decoding method combined with CRC is also given.It can reduce the number of loop iterations adaptively while maintaining the performance advantage.When the SNR is greater than 1.8 dB,the number of iterations can be reduced to less than 2 times,and the system processing speed can be accelerated.4.In 20 M system bandwidth,the baseband development platform verifies that the time required for the system to complete the channel estimation and signal detection process for each subframe is 0.952 ms,which meets the time requirement for data processing in the protocol.The resource consumption rate of FPGA chip is 24%.The Verilog hardware description language is used to FPGA implement for the process modules.Through the ModelSim function simulation and Chipscope online logic timing the correctness of the scheme is verified,through the timing analysis and resource consumption the rationality of the scheme is verified,and through the comparison between the real-time analysis of air interface data and the test user equipment the practicality of the scheme is verified.The design has been applied to the actual project.