Research On The Generation Circuit Of Range Image And Intensity Image Of Geiger Mode APD Focal Plane Array Laser Radar

The non-scanning active imaging Geiger mode APD focal plane array laser radar has the characteristics of fast imaging speed,long detection range and high detection sensitivity,and is suitable for miniaturized target detection systems with high real-time requirements.Since the original distance obtained by this laser radar is relatively low in signal-to-noise ratio,it is necessary to calculate the multi-frame accumulation algorithm to generate a range image and intensity image both with high signal-to-noise ratio,thereby providing more effective information for tasks such as target recognition.In order to ensure the real-time performance of the target detection system,it is necessary to design a dedicated hardware circuit to accelerate the calculation of the multi-frame accumulation algorithm.In this thesis,a circuit scheme with high data throughput rate and interface bandwidth utilization is designed,which realizes the hardware acceleration of multi-frame accumulation algorithm.This circuit scheme is divided into a data-path part and a data stream scheduling part by function.The data-path part proposes a pipelined circuit architecture,which solves the design difficulties of the traditional architectures,realizes design goals such as low-latency and high-data throughput histogram statistics,and the architecture has flexible configurability and stability.Software and hardware stable interaction;There are three introduction points in the data stream scheduling part.Firstly,the bandwidth utilization of the LVDS interface for data transmission is improved by splicing and parsing the laser radar original range image data width.Secondly,the parsed original range image data,under the control of the area-optimized read-write strategy and the hierarchical state machine,realizes the data cache operation of consecutive frames for the low-memory resource consumption,and provides stable data stream for the data-path part.As for the alternative off-chip DDR cache scheme,an optimized DDR memory management method is proposed for the current application scenario,which can further improve the data throughput rate of the circuit.Finally,the single-frame range image and intensity image generated by the calculation of the data-path part are packaged into a unified format data packet by the package logic,and transmitted to the DSP for subsequent processing via the EMIFA bus.In this thesis,the scheme of the circuit is implemented on the FPGA to complete the actual case verification.By cooperating with the DSP,the real-time generation and monitoring of the range image and intensity image is realized under the operating condition of the laser radar detector with 1Kfps frame rate,64*64 pixel array size and 12 bit gray level,which satisfies the delay requirement of this part of the embedded laser radar preprocessing system based on FPGA+DSP.Under the same algorithm condition,compared with the pure software calculation of DSP,there is a speedup of 17.2 times.At the same time,the circuit has a high data throughput rate,a flexible and configurable circuit operation mode,and an efficient and stable software and hardware cooperative interaction capability under limited resource occupation.