Font Size: a A A

Research On Kye Technologies Of Software And Hardware Cooperative Acceleration For SDN/NFV

Posted on:2021-08-05Degree:MasterType:Thesis
Country:ChinaCandidate:S WangFull Text:PDF
GTID:2518306308973439Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
In recent years,with the application of Software-defined Networking(SDN)and Network Functions Virtualization(NFV)technologies,the network architecture has also continuously evolved,which can meet the demand of network flexibility and scalability.However,various virtualized network functions(VNFs)implemented using virtualization technologies cannot meet the performance requirements of future network services for data processing rates and forwarding delays on general-purpose servers.On the other hand,under the SDN/NFV network architecture,network tidal traffic makes the utilization of network resources appear non-uniform in time and space,which leads to excessively high service blocking rates.In order to meet the network's performance requirements for low latency,high flexibility,and large capacity,this paper conducts research on key technologies of software and hardware cooperative acceleration for SDN/NFV,and addresses the contradiction between performance and flexibility of SDN/NFV network devices and network capacity optimization,from the perspective of the underlying hardware technology and the upper-layer software strategy,design and implement a hardware acceleration general architecture based on FPGA and a network capacity optimization mechanism based on VNF deployment to meet the performance and flexibility requirements of SDN/NFV network devices,which improves the service carrying capacity of the network,and achieve the purpose of load balancing of network traffic.The main innovations of this article are as follows.First,this study designs and implements a general hardware acceleration architecture based on FPGA.Aiming at the contradiction between performance and flexibility in SDN/NFV network devices,this paper designs and implements a hardware-accelerated general architecture based on a Field Programmable Gate Array(FPGA).This architecture has the acceleration processing capabilities of both communication-intensive tasks(such as packet forwarding)and computation-intensive tasks(such as data encryption and decryption).It can not only reduce the processing delay of data packets,but also flexibly configure network functions according to business needs and meet diverse server requirements.After experimental tests,the FPGA-based hardware-accelerated general-purpose board has a processing delay of about 0.3 milliseconds and a maximum throughput of 9.68 Gbps.The processing efficiency of VNF data packets gradually increases with the length of the data packets,and the maximum efficiency can reached 96.31%.Secend,this study proposes a network capacity optimization mechanism based on VNF deployment.In order to increase the network service carrying capacity under limited network resources,this paper skillfully uses the uneven utilization of network resources under tidal traffic and the interaction mechanism between network level,and adjusts the convergence layer network VNF deployment to make traffic flowing into the core layer network tend to be balanced,so as to reduce the network service blocking rate and increase the network service carrying capacity.Simulation results show that by adjusting the VNF deployment position in the aggregation layer network,the service blocking rate of the core layer network can be effectively reduced,and the service capacity carried by the network can be improved.
Keywords/Search Tags:software-defined networking hardware, acceleration general architecture, virtualized network function placement, network capacity optimization
PDF Full Text Request
Related items