Design And Implementation Of Hardware Acceleration Architecture Of Physical Layer Protocol Stack Based On FPGA

With the rapid development of mobile communication technology,high capacity data transmission is carried out in the protocol stack,and the amount of data transmission increases accordingly.The system transmission efficiency and running time of the protocol stack have higher requirements.Use the field programmable gate array(FPGA)to realize the LTE user data protocol stacks of downlink Shared channel(PDSCH)link data sender function,and use it as the core of data processing equipment,can effectively improve the performance of the protocol stack system of data processing is suitable for large capacity real-time signal and protocol processing,use of the existing open source OAI platform can achieve the function LTE protocol stack.This paper presents a hardware acceleration architecture of protocol stack based on OAI platform and FPGA.The specific level and symbol level of the physical layer with the ability of big data processing are realized in FPGA,and the functions of the superior network layer including MAC layer are realized in OAI.This paper focuses on the design process of PDSCH data processing process,and carries out the relevant function simulation and verification on the hardware platform.Firstly,based on the operation mode of OAI EPC+OAI ENB+OAI UE,the traditional 3GPP network simulation is implemented.The system architecture of hardware and software combined with FPGA+OAI is designed.The relevant modules are divided and studied under the system architecture,and the relevant functional modules of the system design are introduced.Secondly,the downlink channel data processing process in PDSCH is mainly composed of bit-level and symbol level.The data basis of FPGA simulation test is provided by using OAI.Based on this,the FPGA module is subdivided.Finally,Verilog HDL language is used to implement the FPGA function module.After comparing with the OAI data and referring to the protocol specification,the result of functional simulation is correct,which verifies the correctness of the program,and completes the FPGA program design of the PDSCH sender;The hardware simulation time results are compared with the relevant running time of OAI,which verifies the feasibility of the hardware acceleration architecture of the protocol stack proposed in this paper,reserving more time for the upper layer to carry out complex scheduling algorithm,and alleviating the overall pressure of the system.