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Case Design And Hardware Implementation Of Image Processing Based On High Performance

Posted on:2014-10-10Degree:MasterType:Thesis
Country:ChinaCandidate:J S XiaoFull Text:PDF
GTID:2208330434972840Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Digital Image Processing technology has been widely applied in the field of electronic communications and information processing, and its implementation method is divided into two major categories, software and hardware. Compared to hardware implementation, the advantages of software implementation are that the process is simple, and the progra-mming is flexible. But there exists some disadvantages too, such as the processing speed is slow, and the efficiency is low. Take the demand of real-time image processing in many areas into account, research on its hardware implementation has a strong practical significance.In this paper, first the internal resources in Virtex4, such as clock, DCM, RAM and CLB are introduced. Subsequently, the basic knowle-dge of digital image processing as well as the two algorithms, histogram equalization and53wavelet transform are described in detail. Based on the existing algorithm flow, the two algorithm procedures for Matlab have been designed independently. Meanwhile, the simulation results consisting of the image and the run time have been given.A lot of research work have been done based on Virtex4hardware platform, including the following aspects:(l)The logic design of histogram equalization are implemented using verilog. Here the ping-pong structure is adopted, which is good for par-allel processing. Different registers are used for storing the count, accu-lative results and the mapping results, and so the structure avoids the sequential operation. Tranditional structure consumes0.33ms, while the ping-pong stucture just needs0.22ms, and this shows that the ping-pong structure is good for saving run time.(2) The logic design of histogram equalization are implemented using verilog. A new structure is put forward,. The structure omits the data tr-anspose step during the2D transform. And because of eliminating the need for one step, the run time also can be saved. The results show that the new structure’s processing time is0.98ms, and the traditional struc-ture’s processing time is1.15ms.At the end of the thesis, the algorithm verification and the result analysis has been done on the platform ML402. The results show that the speed of the hardware implementation of digital image processing is much faster than the software method, and the internal resources are reliable, as well as the newly proposed structures in53wavelet transform are effective.
Keywords/Search Tags:FPGA, digital image processing, histogram equalization, wavelet transform, VGA
PDF Full Text Request
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