Research On Soft Error Vulnerability Analysis And Mitigation Method For Microprocessor

With the joint promotion of architecture technology and integrated circuit(IC)technology,the development of microprocessor has been very rapid during the past several decades.Architects usually regard the microprocessor performance as their first priority.The rapid development of IC technology has led to the continuous reduction of the IC feature size,but the accompanying soft error problems have also become unnegligible,and the reliability of the microprocessor is severely affected.Evaluating the soft error vulnerability of the microprocessor in the early architecture design stage can not only provide reference for the architect's later soft error mitigation method design,but also achieve the high reliability design goal at a lower cost.Therefore,it is extremely urgent to study the soft error vulnerability analysis and mitigation methods for microprocessors.The emphasis of the soft error vulnerability analysis of microprocessors is to evaluate the Architectural Vulnerability Factor(AVF).Researchers have proposed several AVF evaluation tools at the microprocessor architecture level,but most of them are not open source and difficult to obtain.Even the open source Sim-SODA still has some limitations,for example,it is not applicable to microprocessors based on the ARM architecture.In addition,seldom can we find in-depth researches on the relationship between structure queue occupancy and AVF values,and thus the soft error vulnerability evaluation cannot be used to mitigate the soft error of structures.Aiming at the above problems,this thesis studies the soft error vulnerability analysis and soft error mitigation methods for microprocessors.The main content can be summarized as follows.1.The research background and significance of microprocessor soft error vulnerability analysis and soft error mitigation method are expounded firstly.Then,the concept,classification and impact of microprocessor soft errors are analyzed,as well as two important parameters,the AVF and the Architectural Correct Execution(ACE).Finally the reliability evaluation indicators required for this thesis are proposed.2.The existing AVF evaluation method is improved to make it suitable for the ARM architecture microprocessors and the accurate soft error vulnerability analysis.Then,the AVF modeling is performed on the SimpleSim-ARM,and an accurate and general soft error vulnerability analysis framework,SSA-SEVA,is proposed.The soft error vulnerability analysis results of various structures of the microprocessor can be obtained by SSA-SEVA,which are the basis for subsequent analysis of the soft error mitigation method.3.The configuration parameters of the non-address-based structures are changed,and the AVF values of the structures under different configurations are obtained through the SSA-SEVA.The result shows that the larger the capacity of the Issue Queue(IQ)and the Register Update Unit(RUU),the smaller the AVF value of the corresponding structure.And the larger the number of functional unit(FU),the smaller its AVF value.In addition,it is verified that the relationship between the IQ queue occupancy and the IQ size is in agreement with the Logistic model.4.A soft error mitigation method based on static compilation is adopted to reduce the queue occupancy by dynamically adjusting the IQ size,thereby realizing the mitigation of IQ errors.Using this method,the AVF value of IQ is reduced by an average of 16.5% and the MITF value is increased by an average of 6.9%.In addition,the AVF is adjusted by matching the instruction mix ratio and the function unit configuration,and the soft error vulnerability of IQ is reduced by shortening the instruction wait-time in IQ.As a result,the AVF value of IQ is reduced by an average of 10.5%,and the MITF value is increased by an average of 11.5%.In summary,this thesis studies the reliability of ARM architecture microprocessor from two aspects,the soft error vulnerability modeling and the soft error mitigation method.The research results can provide a helpful theoretical reference for the future developments and applications of microprocessors.