Register File Soft Error Masking Effect Analysis And Partial Protection Techniques Exploiting

With decreased feature size,increased chip density and lowered threshold voltage,integrated circuits are becoming more vulnerable to external radiation or electrical noise induced soft errors.One of the structures in modern processor based systems where soft errors can be most harmful is register file.However,protect the whole register file can induce a significant area,power and performance cost.As a result,it is meaningful to find an accurate and fast static analysis method to accessing individual register's reliability and explore register file partial protection techniques.We classify the soft error masking and propagation effects into three categories: intra-instruction masking effects,soft error post-masking effects and soft error propagation effects.We introduced the concept of mask window and affect zone.We also described a graph based mask window analysis framework(GBMW)to accurately capture each masking effects.Then we summarized various soft error mitigation techniques,and gave a new register file partial protection architecture,named S-Shield to give priority to those registers with high AVF values while protecting them using error correcting codes(ECC).We verify our method by simulating on GEM5.Experimental results show that GBMW decreases the average error rate of predicting soft error masking effects to 57% of the traditional method that takes no masking effect into account.And S-Shield achieves on average 23% the reliability improvement compared with traditional ECC protection architectures.