Research On Key Technologies Of JESD204B Protocol

With the rapid development of the IOT technology and 5G technology,the number of data to be transmitted in the communication network has increased dramatically,and this situation leads to the desire for a higher transmission rate.Due to the disadvantages,such as the complicated PCB layout,a large number of package pins,serious crosstalk between lines,and high power consumption,parallel interfaces(CMOS and LVDS)cannot meet the demand for high-speed data transmission.In this context,the JEDEC Association released the JESD204B protocol in 2011,which enables high-speed communication between data converters(ADC/DAC)and data processing devices(FPGA/ASIC).Compared with the parallel transmission interface,the serial transmission interface based on the JESD204B protocol has the following advantages:low power consumption,low cost and low design complexity;supporting multi-lane,multi-link and multi-chip synchronization;supporting deterministic latency;employing a more flexible device clock;data rate being up to 12.5 Gbps/lane.Therefore,the JESD204B serial interface is gradually becoming the first choice for high-speed data communication interface.In this thesis,the JESD204B protocol is deeply studied.Firstly,the key circuits such as(de-)scrambler,receiver buffer,8B/10B encoder/decoder and test sequence generator are designed,simulated and optimized.Then these circuits are applied to a receiver circuit based on JESD204B protocol,and the function of the receiver circuit is proved correct through verification.Finally,the layout of the JESD204B protocol layer in the receiver circuit is given,and the test results of the chip samples show that their performance meets the design requirements.The main contents and conclusions of this thesis are summarized as follows.1)The main contents of the JESD204 series protocol are briefly introduced,and the working principle of JESD204B protocol and deterministic latency technology are particularly analyzed.2)The overall architecture of the key technologies in the JESD204B protocol is introduced,and the principle of(de-)scrambler,receiver buffer,8B/10B encoder/decoder and test sequence generator in the protocol is analyzed.Based on the previous research,a 32-bit parallel processing scheme is proposed to improve the data processing rate of the link.These circuits were RTL-level designed using Verilog HDL,and verified by Cadence's NCVerilog10.2,the results show that all circuits could realize their functions correctly.The circuits designed in this thesis are applied to a receiver circuit based on JESD204B protocol.3)The RX RTL and TX IP are jointly simulated by the UVM verification platform,and the simulation results of the link establishment process and the timing relationship between clock signals are given,as well as the waveform diagram and log file of the overall simulation of the transceiver.It is verified that the RX RTL function is implemented correctly,and also proved that the circuits designed in this thesis can work together correctly.4)Based on 65 nm CMOS process,the layout of the receiver circuit is designed using Synopsys'ICC2,and the area of the JESD204B protocol layer layout in the circuit is approximately 1100×4400?m~2.The chip sample is tested by the test platform after it is made.The test results of 2.5 GHz and 2.0 GHz input are given,and the spectral characteristics and time domain characteristics of the output data are analyzed.The test results show that when the output frequency is 20 MHz,the highest sampling rate of the sample is 2.5 GSPS,the maximum value of SFDR is-72.46 dBc at this sampling rate,and the data rate is 6.25 Gbps/lane;at a sampling rate of 2.0 GSPS,the maximum value of SFDR is-69.38 dBc,and the data rate could reach up to 10 Gbps/lane.Compared with related domestic research and products,the receiver chip is more advanced in data processing rate.There are two innovation points in this thesis:first,a 32-bit parallel(de-)scrambling algorithm is proposed and implemented to improve the data processing rate and reduce the clock frequency requirement;second,a test sequence generation circuit is designed,which can generate test sequences of different types and bit widths.These sequences can be used to test the circuits in JESD204B,which can shorten the test time and improve the test efficiency and accuracy.