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Research And Design On The Key Technologies Of Time-Triggered Ethernet

Posted on:2020-09-26Degree:MasterType:Thesis
Country:ChinaCandidate:J X WangFull Text:PDF
GTID:2428330575966213Subject:Electrical engineering
Abstract/Summary:PDF Full Text Request
Time-triggered Ethernet is a time-deterministic network which is compatible with standard Ethernet.It has unique advantages in industrial control,such as high real-time,high reliability and high fault tolerance.The advantages make the time-triggered Ethernet be a research hotspots in the real-time industrial control field and attract the attention of many experts at home and abroad.At present,there is a huge gap in time-triggerd Ethernet field between domestic technology and foreign countries.This paper conducted in-depth research on the key technologies of time-triggered Ethernet,including schedule problem solving,transmission delay of BE messages,AS6802 time synchronization protocol and so on.The main contributions of this paper are as follows:1)We studied the solving problem of the stable schedule,and transformed its constrasints into mathematical models.We proposed a solving method of schedule based on particle swarm optimization(PSO)algorithm,and optimized the convergence process of the PSO to speed up the convergence and avoid falling into local optimal problems.2)We studied the transmission delay of BE messages in time-triggered Ethernet.In order to reduce the latency time in the case of densely arranged condition of TT tasks,we proposed the"back to back" schedule solving strategy and compared with the tradition strategy"schedule porosity".We compared the effects of the two strategies on transmission delay of BE messages using OMNeT++.3)We studied SAE AS6802 time synchronization protocal in depth,and introduced the work and algorithms of different nodes in detail.We implemented the protocal based on FPGA,which lay the foundation for the implementation of time-triggered Ethernet nodes.4)We proposed the framework of the MAC layer design of nodes in time-triggered Ethernet.We carried out the transmission of TT,BE and PCF frames to computer successfully based on FPGA,which lay a foundation for the further development of mature TTE nodes.
Keywords/Search Tags:time-triggered Ethernet, stable schedule, end-to-end transmission delay, AS6802, clock synchronization, MAC layer design
PDF Full Text Request
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