Design And Implementation Of AS6802 Time Synchronization Protocol Based On Time-Triggered Ethernet

With the development of distributed systems,the real-time,reliability,and high security requirements for data exchange between devices in the system are more urgent,making it impossible for Ethernet technology to be applicable to the corresponding business areas.Time-triggered Ethernet combines the real-time and determinism of time-triggered technology with the advantages of traditional Ethernet to effectively solve the disadvantages of traditional Ethernet that cannot meet high real-time and reliability requirements.It is widely used in aerospace,industrial control and other fields with high real-time and high security requirements.Since the real-time and determinism of time-triggered Ethernet is based on a highly-accurate globally synchronized clock,accurate time synchronization is the basis of time-triggered Ethernet technology research and has important research value and broad application prospects.The open standard AS6802,published in 2011,defines a synchronization technology that is deterministic,highly fault-tolerant and non-blocking.After studying the open standard AS6802 protocol standard and the existing Ethernet time synchronization scheme,this paper firstly adopts the hardware and software co-design platform of FPGA+ARM,independently designs and implements the time synchronization unit integrating the three functional units of SM,SC and CM,and describes in detail the design of each functional module in each synchronization unit implemented by FPGA.Then,in the Model Sim simulation environment,functional simulation was performed on each major module;finally,the system was measured in a Gigabit Ethernet environment,and the synchronization accuracy was better than 20 nanoseconds.Because the receiving and sending modules implemented using FPGAs replace the MAC IP cores in the existing Ethernet time synchronization scheme,the system is more flexible in the reception and transmission of Ethernet frame data,and reduces the dynamic delay introduced by the MAC IP core.Makes the synchronization more accurate,and has the characteristics of low cost,easy to transplant.