Research On The Key Technologies Of Time-Triggered Ethernet And Core Module Design

Industry 4.0 and Made in China 2025 have brought great revolutions and challenges for Chinese industry.In the process of advancing smart factory,the growing demand for networking means more complex network cabling,more congestion of information transmission and higher costs.Therefore,it is very important to find a network protocol with high flexibility,compatibility and high precision.Among those new types of real-time Ethernet,Time-Triggered Ethernet(TTE)is widely concerned by researchers at home and abroad due to its superior performance.This article focuses on the study of Time-Triggered Ethernet key algorithms and design of components.The main work includes analyzing data transmission mechanism,designing message scheduling algorithm and implementing synchronization technology,which solve the most critical technical problems to break down foreign technical barriers and design TTE products with independent property rights.First of all,with the aid of OMNeT ++ emulation platform,the mechanism of time-triggered Ethernet data transmission is analysed and simulated.The main work is extending the standard Ethernet module INET by setting up publish-subscribe system,adding MAC relay unit and establishing delegator module.Therefore,the TTE data transmission control mechanism is realized.The implementation of this design also provides specific design ideas for developing FPGA-based TTE nodes.Secondly,this thesis completes the design of two core arithmetic modules based on the research and innovation of existing algorithms.For the tt-scheduling problem,this paper mainly constructs the network interconnection matrix and communication task matrix,transforms various constraints including contention-free constraints,application-level constraints,path-delay constraints and other hardware restricts into a cost function.This paper proposes a simulated annealing particle swarm optimization algorithm(SA-PSO)to solve the problem above.This algorithm is an improvement of the traditional particle swarm optimization,which gives more possibility of solution space and avoids the local optimization,and it can also accelerates the convergence speed to a certain extent.It is a heuristic algorithm with excellent performance.For the time synchronization algorithm,this paper combines with three major AS6802 algorithm,timing maintenance,centralized collection and clock calibration algorithm.In the meanwhile the fault-tolerant mechanism,cluster detection,multi-domain synchronization and other functions were also optimized and improved.Finally the node model equipped with TTE synchronization function is completed based on FPGA,which lays the foundation for further development of hardware products with complete TTE functions.Finally,based on the above node model,a small synchronous network is constructed and a detailed simulation scheme is designed.The model is verified to have the expected microsecond synchronization precision and good fault tolerance.