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Research On Key Technologies For Wireless Communication Reliability In WiNoC

Posted on:2020-10-31Degree:MasterType:Thesis
Country:ChinaCandidate:L Z HuFull Text:PDF
GTID:2428330575496895Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
With the continuous development of semiconductor manufacturing and design proc esses,the number of on-chip cores continues to increase,the network radius continue s to grow,and the average transmission distance of data packets continues to grow.Th e on-chip network architecture of traditional planar metal interconnects has graduall y experienced high network latency,high power consumption and low throughput.Co mmon 3D on-chip networks,optical interconnected on-chip networks,and RF interco nnected on-chip networks are limited by their own shortcomings,making it difficult t o meet the current multi-core system requirements for throughput,latency,and powe r consumption.In the end,researchers turned their attention to wireless on-chip netwo rks.With the deepening of research by researchers,wireless on-chip networks have be come the main solution for on-chip interconnect architecture with its good network pe rformance and low power consumption.However,the wireless link in the wireless onchip network has high error rate due to its inherent transmission instability,which seri ously affects the reliability of on-chip communication.This paper conducts an in-dept h study on the reliability of wireless communication in wireless on-chip networks.Th e main work of the thesis is as follows:(1)In the wireless on-chip network,due to crosstalk between lines,noise and transi ent faults,the reliability of data packet transmission in the link faces great challenge s,which seriously affects the overall performance of the network.Therefore,the faulttolerant design of the link appears.Especially important.To solve this problem,this p aper proposes a new hybrid fault-tolerant model.This model designs an improved En d-to-End retransmission mechanism for the transient failure of the wired link,classifie s and encodes the packet header microchip and the body microchip,and enhances th e network fault tolerance.For the wireless link transient fault,The traditional Switch-t o-Switch scheme is applied to wireless links.The experimental results show that thi s paper adds a small amount of area and power consumption compared with the traditi onal fault-tolerant scheme,but has achieved an increase in network throughput and lat ency.(2)Due to the inherent transmission defects of wireless channels in wireless on-chip networks,the reliability of wireless communication is seriously threatened.How t o ensure the reliability of wireless communication faces great challenges.In additio n,the traditional fault-tolerant solution based on the error recovery strategy will brin g a lot of retransmission overhead in the case of high failure rate,which seriously affe cts network performance.Therefore,this paper designs a new fault-tolerant scheme ba sed on error avoidance strategy.The solution dynamically adjusts the voltage and freq uency in the network based on the real-time status of the network,thereby reducing th e occurrence of faults.Experiments show that compared with the traditional fault-toler ant scheme based on error recovery strategy,this paper achieves a large performance i mprovement with less power consumption and area overhead.
Keywords/Search Tags:wireless on-chip network, fault tolerance, error avoidance, dynamic voltage frequency
PDF Full Text Request
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