Semi-modular Semantic Of Logic Gate Circuits Based On Interleaving Mode

In the past two decades,asynchronous circuits with their advantages over synchronous circuits: no clock skew,higher reliability,better integration potential,show considerable potential in areas such as microprocessors and low-power circuits.However,the inherent concurrence of asynchronous circuits makes them also difficult to verify.The number of execution paths can be very large because of the variation of the component and wire delays.Thus,a proper circuit behavior must be assured for all the possible execution paths.This paper adopts a state-based approach.According to the state transitions of the circuit,a partial order relationship on cumulative state vectors is obtained.The poset can describe the asynchronous circuit in more detail.Besides,the characteristics of state changes in the circuit can be reflected through vector operations.Semi-modularity is an important property in the design of asynchronous circuits.It is closely related to the hazard-free circuits.This paper checks the semimodularity for the circuit model based on the interleaving mode.The semi-modular lattice semantics of logic gate circuits are discussed in detail.In view of fact that the number of states in the circuit will increase exponentially,algorithms for generating Hasse diagram automatically,as well as verifying the semi-modularity of designs are proposed.Finally,the applicability of the verification method has been tested with the example of C-element.