Structure Design And Numerical Simulation Of 4H-SiC Power MOSFET

Silicon carbide（SiC）has become an excellent material for the third-generation semiconductor due to its excellent characteristics such as high band gap width,high critical breakdown electric field,high electron saturation mobility and high thermal conductivity.Compared with the Si Metal-Oxide-Semiconductor Field Effect Transistor（MOSFET）,the SiC MOSFET has a faster switching speed and lower switching loss.Lower on-resistance and higher breakdown voltage,widely used in power electronic systems,is the booster of economic and social green development.However,the traditional SiC trench MOSFET（UMOSFET）device and SiC Vertical Double-diffused MOSFET（VDMOSFET）device have their own shortcomings,aiming at these shortcomings,this paper proposes an optimized structure for each structure.In order to improve the performance of the device,this paper mainly does the following work:1.An optimized UMOSFET device structure is proposed.The structure alleviates the problem of concentration of electric field in the p+shielding region in the traditional structure by ion implantation in the MOSFET to form P-type doping region.At the same time,higher concentration and thicker current spreading layer are used to reduce the characteristic on-resistance of the device.A heterojunction diode is integrated in the structure to improve the third quadrant characteristics of the device.After research,the proposed structure is compared with the traditional structure,the device’s figure of merit is increased by about 105%,and the total reverse recovery charge of the device is reduced by about 52%.Finally,a feasible process flow for manufacturing the optimized UMOSFET device structure is designed.2.A 4H-SiC MOSFET device structure（HJD-SG-MOS）with a p+polysilicon integrated heterojunction diode between the split-gates is proposed.At the same time,the electric field at the gate oxide is reduced by forming a P-type doping region near the source surface by ion implantation.Because the bottom of the heterojunction diode is at the same height as the bottom of the gate oxide layer,and the coupling area between the gate and drain is reduced,the electric field of the gate oxide layer is effectively reduced,so that a high concentration of current spreading layer can be formed through epitaxy to reduce the characteristic on-resistance of the device.After research,compared with the traditional MOSFET device structure,the performance of HJD-SG-MOS has been greatly improved in all aspects.The on-resistance of the device has been reduced by 27.8%,and the figure of merit has been increased by 37.3%.The high-frequency figure of merit(R_on,sp×C_gd,sp)is reduced by 87%,the high-frequency figure of merit²(R_on,sp×Q_gd,sp)is reduced by 86%,the total amount of reverse recovery charge is reduced by 54.9%,and the switching energy loss is reduced by 37.3%.Finally,a feasible process flow for fabrication of the proposed HJD-SG-MOS device structure is designed.