Design Of Low Power Serial Communication Driver Circuit Based On FPGA

With the rapid development of the semiconductor industry and integrated circuits,not only the operating frequency but also the integration of chips has gotten fast development,at the same time the power consumption of circuits is also increasing rapidly.However the increase of the power consumption will lead the temperature of the chip to high,which will reduce the reliability of circuit design and stability,increasing the design cost of the circuit.Therefore,power consumption has become a significant constraint for the design of integrated circuit.Usually,the gate clock technology is adopted to reduce the turnover of redundant states in the circuit to realize the low-power circuit design,but the gate clock technology will increase the complexity of the gate circuit while reducing the system power,bring some additional power consumption,and increase the competition risk in the circuit system.In this paper,a new low-power sequential circuit design method is proposed by combining two gate clock technologies based on algorithm optimization and circuit control,and it is applied to the design of serial communication driver circuit.In the part of optimization algorithm design,this paper introduces the analysis and design concept of behavior Karnaugh map to intuitively show the distribution of redundant clock signals of each trigger in the circuit.Then in the circuit structure,according to the state transition characteristics of the circuit system,the reasonable choice by gating circuit built automatically triggers,and a 4-bit torque-type counter is taken as a design example.Compared with the traditional 4-bit torsion ring counter,the new 4-bit torsion ring counter with non-structure,or gate structure and xor structure is found that xor structure can completely eliminate the redundant clock signal in the circuit system,thus reducing the power consumption in the circuit system.Finally,a low power serial communication driver circuit based on FPGA is designed by combining the hardware drive circuit with the gated clock technology,and the overall power consumption of the drive circuit is reduced by eliminating the redundant clock signals in the drive circuit.The new low-power timing sequence circuit and low-power serialcommunication driver circuit designed in this paper are feasible for the timing simulation verification through Quartus II.The design of low power serial communication driver circuit based on FPGA studied in this paper,which can be applied to the design of reducing the power consumption of other driving circuits,and providing some reference for other designers.