Design And Implementation Of High Speed Receiving Circuit For Free-space Optical Communication | Posted on:2020-10-19 | Degree:Master | Type:Thesis | Country:China | Candidate:C Y Shen | Full Text:PDF | GTID:2428330572972130 | Subject:Electronic Science and Technology | Abstract/Summary: | PDF Full Text Request | Free-Space Optical communication has the advantages of high data transmission rate,large capacity,strong confidentiality and strong anti-electromagnetic interference capability.It has become one of the main research hotspots between satellite and satellite communication.The experimental research on real-time large-capacity high-order modulation space laser communication system is still in its infancy.Real-time high-order modulation DSP algorithm implementation,as well as real-time controllable high-speed ADC sampling and large-capacity FPGA hardware circuit design that can meet the requirements of DSP algorithms are all difficult problems to be solved.This paper designs a hardware implementation scheme for real-time 2.5 GBaud PM-QPSK coherent space optical communication system and real-time 10 GBaud PM-QPSK coherent space optical communication system,and completes the real-time 2.5 GBaud PM-QPSK coherent space optical communication system.Experimental test of sensitivity and field communication performance.The main research contents are as follows:1.The design and implementation of the receiving end circuit board of the real-time 2.5 GBaud PM-QPSK coherent space optical communication system is completed.The receiving end circuit board have 4 electric signals after optical coherent demodulation of the 2.5 GBaud PM-QPSK system.High-speed sampling,real-time damage DSP compensation,and high-speed interface to test instruments,providing system synchronization clock.2.Completed the whole board test for the real-time 2.5 GBaud PM-QPSK coherent space optical communication system receiving board,and the software alignment implementation scheme between the four ADCs is given.The back-to-back test and the field test of the real-time 2.5 GBaud PM-QPSK coherent space optical communication system are verified.The 2.5 GBaud PM-QPSK coherent optical communication system has a BER of less than 1E-3 and a sensitivity of-48dbm.3.Completed the design of the receiving end circuit board of the real-time 10 GBaud PM-QPSK coherent space optical communication system.It is expected that the receiving end circuit board has high-speed sampling and real-time recording of four electric signals after optical coherent demodulation of the 10 GBaud PM-QPSK system.Damage DSP compensation function to meet the actual receiving performance of long-distance spatial optical communication. | Keywords/Search Tags: | FSO, PM-QPSK, FPGA, Receiver Board, high speed circuit design | PDF Full Text Request | Related items |
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