Design And Verification Of RapidIO Physical Coding Sublayer

With the growing progress of the computer and multimedia technologies, the system put forward higher requirements for the system high-speed interconnection technonlgy. RapidIO is known for its high rate, low latency and high reliability in the field of general-purpose embedded systems have been widely used. Therefore, Design universal RapidIO physical coding sublayer is of great significance.For project requirement of the processor of MaPU, this paper focuses on the design of a high rate, high bandwidth and high reliability RapidIO physical coding sublayer. The RapidIO physical coding sublayer is responsible for realizing the physical layer packet fields encapsulation, sending and receiving packets, port initialization and error management as well. According to the design indicator versatility and features, completed the overall structure, front-end design, the simulation verification and logic synthesis of the RapidIO physical coding sublayer. The main contents are as follows.(1) In this Paper, on the basis of RapidIO Interconnect Specification Rev2.2, completed in-depth research and analysis of indicator versatility and features of the RapidIO physical coding sublayer, proposed the overall structure of the RapidIO physical coding sublayer, and completed the module division.(2) With the top-down design methodology and modular design concept, completed RTL design of each module, it contains control symbol generation, idle generation, stripe, scramble,8B10B encode, Comma detection,8B10B decode, descramble, distripe, lane synchronization, lane alignment, port initialization, error detect, and error recovery.(3) Build a simulation platform and completed functional verification of the RapidIO physical coding sublayer, after that, accomplished the FPGA implementation. Throughout the simulation of the sending and receiving packets, the initialization of the port and error recovery, it verifies the design is in accordance with the RapidIO2.2version.(4) Completed logic synthesis of the RapidIO physical coding sublayer. Accomplished the constraint of the DC environment, area and timing according to the timing requirements. As the DC report shows, the chip’s size is1.06mm2, the power consume is19.36mW, and the clock frequence is312.5MHz.