Design And FPGA Implementation Of Digital Baseband For Two-Way Radio Based On DPMR

The two-way radio plays an irreplaceable role in the fields of disaster relief,public safety,security control,energy transportation,traffic safety,etc.With the development of communication technology and the increasing demands for functions by users,it is inevitable that the two-way radio should be digitized.The dPMR protocol for digital two-way radio introduced by ETSI in 2005 has the characteristics of low design threshold and low cost.It is suitable in the transition process which for the use of two-way radio from analog to digital.A digital baseband of dPMR two-way radio with hardware logic is presented based on FPGA,and it will be a reference to low-cost dPMR dedicated baseband chip.Firstly,the dPMR standard protocol is studied in detail,and the dPMR protocol stack,basic frame structure,service signaling structure,channel coding technology and channel coding mode of basic frame are described respectively.Then the design of link structure for dPMR digital baseband is carried out,and the key technologies such as shaping filtering,quadrature modulation,differential frequency discrimination,frequency offset estimation and timing synchronization in the link are designed.The timing synchronization algorithm is mainly studied,and a timing estimation algorithm with high accuracy,fast acquisition and good tracking performance for dPMR systems is proposed.Then,according to the application requirements,the overall structure design and module division of the digital baseband are performed based on FPGA,and the sub-modules in each clock domain are implemented.The framing controller and the de-frame controller are designed in the high-speed clock domain to complete the framing and de-frame control.The filter module,preamble detection module and bit synchronization module are optimized in the low-speed clock domain to save a lot of hardware resources.Finally,the simulation verification platform is built with Modelsim to complete the simulation verification.The board-level verification platform is built with Terasic's DE3 development board to complete the FPGA verification.The experimental results show that the whole design functions have been realized,and the performance of the digital baseband receiver is good.The correct de-frame rate of the information frame data is up to 99.8%,when the signal-to-noiseratio of the input signal is 8dB.