Design And Implementation Of FPGA-Based Synchronization System For F-OFDM

F-OFDM is a popular waveform in 5G application scenarios and has received widespread attention in recent years.The F-OFDM system needs to ensure orthogonality between subcarriers in each subband,so there are still strict requirements on synchronization.How to apply the synchronization algorithm in OFDM system to F-OFDM system is one of the research hotspots.At the same time,the hardware design and implementation of FPGA-based F-OFDM system is also one of the important research contents of F-OFDM system.This thesis focuses on the synchronization system of the downlink receiving synchronization of F-OFDM system and its FPGA hardware implementation.The specific contents include the following aspects:Firstly,for a typical synchronization algorithm,including the maximum likelihood synchronization algorithm based on cyclic prefix,Schmical&Cox synchronization algorithm using training sequence and H.Minn synchronization algorithm with improved training sequence,the synchronization performance of them in F-OFDM system is compared and analyzed.The synchronization accuracy and the computational complexity of each algorithm are compared from the perspective of hardware resource consumption.In general,Schmical&Cox synchronization algorithm has a good balance between synchronization accuracy and computational complexity.Secondly,for the FPGA hardware design of F-OFDM synchronous system,a design method with functional modularization and synchronous module replacement is proposed.The design and function simulation of the independent module such as timing synchronization module,filtering module,sub-band data processing module and demodulation module in the receiving link are completed.The design of each module is independent of each other.When a module changes or is replaced,controling and feedback information are not performed on the upper or lower level.In the design of the timing synchronization module,the output implements the ping-pong storage function by adding two RAMs,which can support replacement and data exchange of different clock frequency modules.For the related operations and energy calculations in the module,the design uses a recursive approach to reduce hardware resource consumption.Thirdly,for the feasibility verification of the hardware design of the F-OFDM synchronization system,the FPGA board test of the design system is completed.By using the built-in logic analyzer in Xilinx's Kintex-7 series 325t chip,the waveform grabbing and result debugging of the F-OFDM downlink are carried out,and the synchronous output waveform and the demodulated waveform are tested and verified.The results are consistent with functional simulation results.In summary,the design and implementation of FPGA hardware for F-OFDM synchronous system provides a certain technical support for FPGA implementation of F-OFDM system,which has certain application value.