Hardware Implementation Of Hybrid Mutiple Access Signal Generation And Synchronization Detection

Vehicular ad hoc network(VANET)plays a key role in future intelligent transportation system.It provides the communications among vehicles to vehicles(V2V)and vehicles to roadside infrastructure(V2I).In a VANET,all the traffic information on the road can be transmitted to each vehicle and traffic command center in real time,which is of great significance to solve the current problems of road congestion and traffic safety.In addition,with the fully military mechanization in China,the military application prospect of VANET shows its great potential.The characteristics of VANETs are fast network topology changes,unstable communication channel and limited network capacity.To deal with these challenges,this thesis focuses on the hardware implementation of hybrid multiple access signal generation and synchronization sequence detection.The main work is as follows:Firstly,the research background and current situation of VANET and the basic structure and design process of FPGA are introduced.Secondly,the general framework of the baseband communication system is presented.The frame structure of the IEEE802.11P is modified,and the preamble sequence containing the user information is added to the receiver for the frame synchronization and the user information detection.Then,according to the special structure of the preamble sequence and the good autocorrelation and cross-correlation properties,the algorithm of double correlated peak synchronization detection is introduced.The Matlab simulation and analysis is accomplished.Thirdly,the modules of the hybrid multiple access signal baseband transmitter are introduced in detail,and the hardware design and implementation of each sub module are carried out.Then,the double correlation peak synchronization detection module of baseband receiver is implemented by FPGA,and the theoretical analysis and hardware implementation of carrier frequency offset estimation and compensation module are presented.The whole process includes Verilog HDL design,synthesis,implementation,Modelsim behavioral simulation and Matlab simulation results comparison.In addition,some optimization methods are put forward to optimize the timing and resource consumption of FPGA design,and after the implementation,the timing and resource consumption of the whole design are analyzed.Finally,the ChipScope Pro Analyzer online logic analysis tool is used to complete the online test of the hardware modules of the mixed multiple access signal generation and synchronization detection,and the test results are analyzed.The results of the testing show that each module can work normally.