Research On Synchronization Technology Of OFDM Signal And Implementation With FPGA In Complex Environment

In recent years,the demand for wireless communications in various specific subdivision scenarios has been increasing.In these scenarios,in addition to being affected by multipath effects and doppler frequency shifts,wireless communication systems may also be affected by malicious interference signals,and the communication environment is becoming increasingly complex.In this thesis,based on orthogonal frequency division multiplexing?OFDM?communication link model,the timing and frequency synchronization and the FPGA implementation of the methods are researched.These synchronization methods aim at channels containing several typical time-frequency domain interferences such as single-tone interference,narrow-band interference and time-domain pulse interference.The first chapter of the thesis mainly introduces the background of research and the current mainstream OFDM synchronization methods.In the second chapter,the channel and interference model are described.Meanwhile,the OFDM link model and the waveform frame structure of signal transmission are introduced in the chapter.The third chapter mainly discusses the timing synchronization and frequency synchronization in complex communication environment.The large carrier frequency offset,interference signal and multipath effect are adverse effects to synchronization in complex communication environment.To solve this problem,the sensitivity of carrier frequency offset to Zadoff-Chu?ZC?sequence is analyzed and an improved timing synchronization algorithm is proposed in this chapter.This algorithm overcomes the negative impact of frequency offset to ZC sequence by means of partial cross-correlation accumulation of multiple ZC sequences.The normalized correlation peak value is greater than 0.8 within range of?1 subcarrier frequency offset.The simulation results in different scenarios showed that:if the channel is within typical malicious interference,the timing acquisition probability is greater than 99%when SNR is more than 4dB under the AWGN channel and SNR is more than 8dB under the fading channel.After that,a frequency offset estimation method based on phase difference is also presented in this chapter.This method is the joint estimation with long and short sequences and the estimated range of this method is?1 OFDM subcarriers.The simulation results of frequency offset estimation showed that:in the AWGN and fading channel within typical malicious interference,the root mean square error?RMSE?of estimation are less than 1%when SNR is more than 2dB.The results prove the timing and frequency synchronization methods meeting communication requirements.The fourth chapter of the thesis studies the hardware implementation of synchronization method.Firstly,this chapter introduces the FPGA hardware implementation platform based on Xilinx XCV7690T chip.After that,the FPGA implementation method of timing and frequency synchronization are discussed in detail.The implementation model of timing synchronization mainly contains sliding correlation calculation,correlation peak acquisition and timing tracking.The implementation method of frequency synchronization mainly includes the frequency offset estimation based on CORDIC IP core and the smoothing filter implementation method through multiplexer.Meanwhile,the simulation results based on Modelsim and the testing results of integrated circuit are presented in this chapter.The results show that the calculation delay and resource consumption of the synchronization methods are appropriate to meet the system design requirements.Besides,the correctness of the implementation scheme is verified,for the errors are less than 10^3-between the testing of implementation and the floating-point simulation of the algorithm.Finally,the synchronization method and implementation are added to the OFDM link in the fifth chapter.The performance of the packet error rate of data transmission is simulated in different scenarios and tested on the system hardware platform.Compared with the simulation results,the largest performance rollback of system test is less than2.5dB that to meet the communication requirements.