Research And Design Of SAR-VCO Hybrid A/D Converter

With the development of the digital internet era,analog-to-digital converter(ADC)plays an irreplaceable role that connects the world to the digital world.The continuous shrinkage of CMOS technology has brought about rapid development of integrated circuits.Designing a high-accuracy,high-speed,low-power,small area ADC is a trend and a challenge these years.However,it is very difficult to achieve a multi-function ADC at the same time.In practice,we need to compromise on various parameters.According to different application scenarios,we need to design an ADC with optimal performance.Thus,ADCs satisfying different applications are born one after another.This article mainly studies a new hybrid structure SAR-VCO ADC.The first stage uses the SAR ADC structure and the second stage uses the VCO-based ADC structure.First,this paper analyzes the basic structure,the basic working principle and the key technologies of SAR ADC,VCO-based ADC and SAR-VCO ADC.Secondly,the system-level modeling of SAR-VCO ADC which is designed as a guide to design circuit is performed.Considering factors such as linearity,area,phase noise and power consumption,a two-level optimal bit combination scheme is proposed.According to the results of the behavioral modeling and simulation,the SAR-VCO ADC can be obtained by the 6-bit SAR ADC and the 4-bit VCObased ADC as the optimal resolution allocation scheme.It also provides the theoretical basis and scheme for the subsequent transistor level design.After the theoretical analysis of the system,the circuit of each module of the SAR-VCO ADC has been deeply studied and designed.The first stage uses an asynchronous control SAR ADC architecture and low-power design techniques to reduce power consumption,such as energy-saving capacitor switching procedure,dynamic comparator,dynamic SAR control logic and asynchronous logic control circuits.After the first stage of quantification is finished,the SAR ADC quantification residue is converted into a current signal as a second level input by the V/I converter.The second-stage VCO-based ADC uses a current-mode ring VCO structure to convert the residual signal into an oscillating signal.The two-stage D flipflop are used to sample the oscillation output signals of two adjacent moments respectively.Then an XOR gate is used to implement differential operations on the sampling results to complete the quantization function.Subsequently,a digital coding circuit was precisely designed to uniformly output the digital output code of the two-stage ADC to realize the SAR-VCO ADC conversion function.This article designs a two-stage hybrid SAR-VCO ADC chip,using SMIC 0.18?m CMOS technology,at a 1.8V power and 25MS/s sampling conditions,the ADC's ENOB is 8.36 bit,SNDR is 52.1dB,SFDR is 63.4dB,power consumption is 2.57 mW.