High Speed ECC Research And FPGA Realization In Satellite Communications

After the development of more than half a century, satellite communication hasgradually become an important scheme for many applications, including long distancecommunications, military communications and personal communications. As aneffective technology which guarantees the reliable transmission, ECC (Error CorrectCode) has been developed from the convolution code to RS code, Turbo code andLDPC code, and toward code combination.For its strong error correction ability, convenient construction and simple encoding,conventional RS (Reed Solomon) code is one of ECCs commonly used in satellitecommunication. Among various RS codes, RS (255,223) recommend by CCSDS isespecially widely used. In view of the demand of growing data rate of the satellitecommunications, this thesis designed a high-speed RS encoder and decoder by using theglobal reverse clock and an modified multiplier without more hardware resourcesconsumption. Results show that the throughput of the encoder is4.48Gbps, and thethroughput of the decoder can be up to2.96Gbps.On the other hand，the low density parity codes (LDPC), which can approximatelyreach the Shannon limit, have become the hot spot in satellite communications, and waswidely used in the latest satellite standards, such as CCSDS, DVB-S2, et. al. For theLDPC used in DVB-S2, it is difficult to be realized due to its long code word and various code rates Inview of the huge resource consumption and low throughput of data, a high-speed parallelLDPC decoder is proposed for its FPGA realization by using the normalized sum-rate algorithm. With180parallels,6bit widths and20iterations, the decoder can support a frequency as high as208.9MHz and athroughput of340Mbps according to our testing results in Xilinx SC5VSX95T. In addition, thenewly-designed decoder is compatible with other DVB standards.