Implement Of LDPC Codes In FPGA

Today one of the hottest topics in coding theory is Low-Density Parity-Check(LDPC) codes. Originally invented in the early1962by Gallager, LDPC codes wereforgotten. They experienced an amazing comeback in the last few years. LDPC codesare not only attractive from a theoretical point of view, but also perfect for practicalapplications. Quasi-Cyclic (QC) LDPC codes are a subclass of LDPC codes and playan important role in that. These codes have encoding advantage over other types ofLDPC codes.This project aims to implement a working version of LDPC codes in FPGAefficiently. It means that we already have the information bits and what the LDPCencoder in FPGA needs to do is to process the information bits and output the codewords. The comprehensive study on the related field should be carried out to verify thecorrectness of the code word generated by the FPGA. This process of verification canbe realized by an equation (it will be discussed later). If all possible information bitsand their corresponding code words satisfy the equation, then we can confirm thecorrectness of encoding process.The full text is totally divided into five chapters, the concrete research contentsof each chapter is:Chapter1Preface. This chapter introduces the choose basis、study backgroundand meaning of the LDPC, and finally discusses generally the research content andthe expected results.Chapter2Introduction of QC-LDPC Codes.In this chapter, the concept ofQC-LDPC code is introduced. We have presented method for finding the generatormatrix of a QC-LDPC code whose corresponding parity-check matrix is given as anarray of circulants. The NASA’s standard for parity-check matrix and generatormatrix[5]is interpreted.Chapter3Realization of QC-LDPC algorithm.As we have discussed four kinds of algorithm for QC-LDPC encoding and analyzed the hardware requirement andencoding time. These implementations require a complexity linearly proportional tothe number of parity-check bits of the code for serial encoding, and to the codelength for high-speed parallel encoding. Give the speeds and complexities of variousencoding circuits. Each encoding circuits can be implemented to provide varioustradeoffs between speed and complexity.Chapter4Hardware design of QC-LDPC.In this chapter, hardware selection isdiscussed and the hardware structure is presented. For further interpretation, theevaluation platform ML401and its key features involved in this project areintroduced.Chapter5Implementation and results.In this chapter, the implementation ofencoder is discussed with details. The software used and the method to get someimportant data are presented. The procedure for implementation of encoder isintroduced step by step. Then a method for verification is introduced and carried out.10sets of random information sequences are used to test the implemented encoder.Their corresponding code words are analyzed as correct. That is to say, theimplement of LDPC encoder is carried out and proven to work, fully met projectgoal.The goal of the project is to efficiently implement a working version of LDPCencoder in FPGA. Several QC-LDPC code encoding algorithm are introduced andtheir encoding speed and cost are analyzed and compared.A SRAA-based parallelencoder following the encoding standard provided by NASA is simulated oncomputer and implemented in Virtex4, an FPGA which is manufactured by Xilinx.To form this encoder,28511-bit cyclic shift registers,14308two-input AND gatesand14306two-input XOR gates (or two7154-input XOR gates) are needed. Timeneeded for encoding is511clock circles. As the clock for this FPGA is100MHZ,encoding is carried out in511×10ns=5.11us.To verify the correction ofimplementation, the generated code word is transmitted into a computer for analysis.RS-232port is implemented to form the transmission of code word.10sets ofrandom information sequences are used to test the implemented encoder. Theircorresponding code words are captured and then analyzed as correct. The implementof LDPC encoder is carried out and proven to work, fully met project goal.