Application Of TNoC-Based Trace And Debug System In Baseband Chip

MPSoC technology has been widely used in high-performance SoC design,because they can solve the contradiction between performance requirement and power consumption.However,the increase in complexity and scale of MPSoC has brought huge pressures on verification,debugging and testing.The intense development cycle and the existence of uncertainty errors make it more difficult to guarantee zero defect in the first tape-out.Thus,It's crucial to find and locate defects quickly in the post-silicon stage.Using debugging technology to locate and analyze defects has been becoming the key to reduce cost.MPSoC technology has been widely used in high-performance SoC design,because it alleviates the contradiction between performance requirements and power consumption to some extent.However,the increase in complexity and scale of MPSoC has brought huge pressure on verification,debugging and testing.The intense development cycle and the existence of uncertainty errors make it more difficult to guarantee zero defect in the first tape-out.Therefore,it's crucial to quickly find and locate defects in the post-silicon stage.Finding and analyzing defects with debugging techniques has been becoming the key to reducing debugging costs and time.The existing Debugging and Tracing systems are generally based on multi-buffer arbitration and a shared No C structure.With the increase in the size and complexity of MPSoC design,existing solutions have been difficult to meet the bandwidth requirements of MPSoC multi-core real-time concurrent tracing and data transmission,and there is a deep contradiction between bandwidth and debugging design overhead.In order to solve the above problems,this paper introduces a TNoC-based on-chip tracing data transmission solution and applies it to a baseband chip.This paper first analyzes the requirements of the MPSoC development for the post-silicon tracing and debugging technology,and summarizes the existing hardware debugging techniques.Combined with the baseband chip project that I participated in the internship company,I deeply analyzed the application of the TNoC-based tracing and debugging system.Starting from the structure design of each component of TNoC,the design and working principle of the TNoC specific network interface,general network interface and other components were studied.Through the introduction of a unified source dedicated network interface and MSRAM interface protocol to improve the scalability and reusability of the debug structure.We also introduced a double buffer structure in the source dedicated network interface to improve the receiving rate of tracing data.At the same time,the TNoC topology,packet switching technology,port data buffer strategy and flow control mechanism were also studied.By introducing the TNoC link,the IFL protocol and the TNoC packet format,the TNoC design and application features are thoroughly analyzed.To meet the needs of signal level tracing and debugging requirement,a novel monitor module is introduced,which improved the flexibility of signal monitoring.In order to meet the requirements of MPSoC for flexible screening,classification and storage of tracking data in different debugging scenarios,the MBT module was introduced.At the same time,the tracing data compression module based on deflate algorithm was introduced to make more efficient use of storage space.Two DnT systems were compared and analyzed from the perspective of structure,performance and area.And we draw the following conclusions: In terms of structure,the structure based on TNoC adopts a unified and configurable dedicated network interface,and due to the distributed feature of TNoC as well as the CDC feature of generic network interface,TNoC-based scheme obtained better scalability and reusability.In terms of performance,the analysis from the performance simulation based on System C model indicate that TNoC solution can better meet the bandwidth requirement.In terms of area cost,the TNoC-based solution has an obvious advantage.Compared with the multi-buffer arbitration based solution,it saved 63% of the buffer cost.Although the logical cost increased by 50%,it still saved about 35% of the total area cost.