Integrate Circuit Trace Data Compression And Debug Trace System Design Research

With the rapid development of the semiconductor technology,hundred millions of transistors are integrated in one single chip.The multi-power domain,power consumption,network throughput,clock synchronization and other issue made MPSoC design complex.Meanwhile if the verification for the chip design is without any scenario constrain,the test vectors can be regarded countless in the limited project life cycle.In order to guarantee the time to the market,the verification plan has been made with some constrains,which make every module and subsystem validation with risks.Thus it is possible to find the verification holes during the post silicon validation and development of platform.When the internal node of silicon chip is difficult to be observed,the information is not easy to be obtained from outside,the post silicon validation would become quite hard.In order to improve the capability of post silicon debug and bandwidth for trace data,the research has been done,and achievementsof this dissertation are outlined as follows:In this work,a novel monitor signal selection mechanism has been proposed.The method give up the distributed monitor selection registers in each subsystem,instead of centralized selection registers,the broadcast selection mechanism is designed.Using these centralized selection registers defined in one module,all the monitor signal on chip can be selected to the pins.The calculation results show the newly designed method can use less register resources,as the monitor signals increase,the centralized selection registers number grows in linear mode,while the distributed monitor selection registers grows in exponential mode.The monitor signals in the work are connected to the on-chip logic analyzer,which can be investigated by the analyzer and improve the whole chip debugging capability.It is quite necessary to have the data trace when doing the system debug due to current complex chip design.In order to improve the observability of the real time system,the research work for arbiter based trace system,bus configure based trace system has been done.For the arbiter based trace system,the variable speed FIFO is introduced to deal with timestamp issue.Read threshold and timeout mechanisms are also designed to improve the data bandwidth by reducing high frequency DDR access and keep the integrity of the data package.Finally,the unidirectional NoC trace system is proposed to increase the trace data bandwidth and decrease the network latency.The newly proposed architecture make the MPSoC real-time trace and debug more efficiency.Test data show:compared with arbiters trace system,the proposed architecture has 40%bandwidth increase and at least 3 times network latency reduction;compared with shared-NoC trace system,the proposed architecture has 27%bandwidth increase and at least 5%network latency reduction.The implemented unidirectional NoC trace system improve the debug efficiency,accelerate the develop life cycle.The output module for the trace system has also been designed.The output module for trace system including two main data paths:trace data output to DDR and trace data output to the pins.In the output stage,the configurable filter rules and sorter are designed,the trace data can be reduced by the combinational rules which decrease the pressure of output data.The trace data encoder is designed according to the industry standard STP2.2,the trace data can be sent out by MIPI protocol,the data can be decoded and analyzed offline.The trace data can also be out by pins thought parallel trace interface.Due to the data is sent out by both clock rising and falling edge,the output data rate is double.After the introduction of novel trace architecture,the compression module is present to improve the data bandwidth further.The compression for the trace data including program instruction reduce and trace data compression.Decrease the storage of instructions is an importance step of instruction compression.The sequential executive instructions take a big percentage in the compiled program,only do the record of program entry and branch would save lots of storage space for trace.For the compression of the trace data,the paper propose a lossless compression method,the hardware circuit is implemented to do the high ratio data compression.The compression module is located at the output stage of the trace system instead of each trace sources,therefore the chip area is saved due to only one compression engine is needed.The compression circuit is implemented according to Deflate algorithm.The first compression stage LZ77 circuit employ dual hash,four data parallel comparisons,which increase the compression ratio.In order to save the hardware resource,the second compression stage Huffman encoding employ the static lookup table to do the compression.The compressed data is packaged in the output stage to keep its integrity.The compression module is verified by the FPGA,and in the finally post silicon test,it can reach above 50%compression ratio in average.The JTAG protocol for debug is researched in the paper.Based on the JTAG protocol,the bridge logic for general industry interface as USB and PCIE are proposed.In the MPSoC,the multi-core trigger matrix,multi-core suspended system and core dump are designed.By using the multi-core debug architecture,it can restore the buggy scenario as much as possible,keep register status,and do the online and offline debug by the master CPU.In the last part of the paper,the mixed signal debug and self-testing design are introduced.Based on IEEE 1149.4,the mixed signal test circuit has been analyzed.Then the Build In Self-Test(BIST)for RF circuit is present to reduce the testing cost.Low cost RF BIST design has become the key issue for the complex receiver and transmitter design.Current architecture take too much resource on and out of chip leading to the high test cost.The BIST architecture proposed by this paper mainly take usage of on chip instrument,the SNR and other test results can be obtained with the help of on chip DSP,CORDIC and ADC.The results can be regarded as key parameter for circuit testing.In the other hand,the self-loop back structure are used to make the on chip generated high frequency signal as test tone,which decrease the influence from outside environment.The proposed method can decrease the hardware overhead effectively and have already been used in chip mass production.