The Design And Implement Of On-Chip Realtime Debug Structure Of YHFT-QDSP

The integration of on-chip debug logic is very necessary with the development of the processor. Moreover, the on-chip real-time debug is more important when the multi-cores SoC appears. It does not need to break the running of the SoC. At the same time, the programs' developers still could analyze the executing scene.YHFT-QDSP is a multiple-core System-on-Chip (SoC) which consists of four YHFT-DSP cores and one X-RISC core. The ways used in the YHFT-DSP and RISC, such as breakpoint and step, do not support multiple-cores SoC very well. In this paper, we design and implement the on-chip real-time debug structure of the YHFT-QDSP. The main research and achievements are listed follow.1. According to the study of the other real-time trace architectures and the IEEE-ISTO standards about debug, design the on-chip real-time debug structure of the YHFT -QDSP,2. Use the verilog HDL to implement the on-chip hardware of the YHFT-TraceDo, which takes in charge of capturing, encoding, buffering and exporting the programs' path information of the YHFT-QDSP. In addition, define the exporting protocol, so the off-chip software would replay the messages that generated by the hardware of the YHFT-TraceDo.3. Establish the chip-level and module-level environment to simulate and verify the on-chip hardware of the YHFT-TraceDo. Otherwise, the results of the simulation are briefly analyzed.4. Verify the YHFT-TraceDo with hardware-software co-verification to make sure the YHFT-TraceDo works correctly.5. Synthesize the on-chip hardware of YHFT-TraceDo after optimized by the methods discussed in this paper. It could reach 400MHz. And the area of it is 668636.3μm~2 . It is less than 1% of the total area of YHFT-QDSP .